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Integrated Circuit

A technology of integrated circuits and dielectric layers, applied in circuits, electrical components, semiconductor/solid-state device components, etc.

Active Publication Date: 2016-12-07
STMICROELECTRONICS SRL
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Providing such a high aspect ratio without introducing the problems associated with open yield and increased contact resistance is a challenge

Method used

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Examples

Experimental program
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Effect test

Embodiment Construction

[0019] now refer to Figures 2A-2D , shows a configuration of contacts according to an embodiment of an example implementation of a MOSFET device 110 used as an integrated circuit. Figure 2A-2B are parallel cross-sectional views offset from each other in the direction of entering / leaving the page. Figure 2C-2D are parallel cross-sectional views offset from each other in the direction of entering / leaving the page, where Figure 2C-2D view with Figure 2A-2B The view is orthogonal.

[0020] Substrate 112 supports MOSFET device 110 . In this example, the substrate is of the silicon-on-insulator 112 type, which includes a substrate layer 114, a buried oxide (BOX) layer 116, and a semiconductor layer 118 (although it will be understood that the features disclosed herein are equally applicable. In the manufacture of integrated circuits that use bulk semiconductor substrates or other semiconductor substrates as supports). The active region 120 for the transistor device is bound...

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PUM

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Abstract

The invention relates to an integrated circuit. A semiconductor substrate includes a doped region. A premetallization dielectric layer extends over the semiconductor substrate. A first metallization layer is disposed on a top surface of the premetallization dielectric layer. A metal contact extends from the first metallization layer to the doped region. The premetallization dielectric layer includes sub-layers, and the first metal contact is formed by sub-contacts, each sub-contact formed in one of the sub-layers. Each first sub-contact has a width and a length, wherein the lengths of the sub-contacts forming the metal contact are all different from each other.

Description

technical field [0001] The present invention relates to integrated circuits and in particular to forming metal-filled vias, trenches or contact openings in metallization (M), pre-metallization (PMD) or interlayer dielectric (ILD) layers of integrated circuits. Background technique [0002] Referring now to FIG. 1 , there is shown the general configuration of a conventional metal oxide semiconductor (MOS) field effect transistor (FET) 10 device. Substrate 12 supports the transistor. In this example, the substrate is of the silicon-on-insulator substrate 12 type, which includes a substrate layer 14 , a buried oxide (BOX) layer 16 and a semiconductor layer 18 . Active region 20 for the transistor device is bounded by shallow trench isolation 22 penetrating layer 18 around the periphery. Within the active region 20, the layer 18 is divided into a channel region 30 which has been doped with a dopant of the first conductivity type, a source region 32 which has been doped with a ...

Claims

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Application Information

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IPC IPC(8): H01L21/768H01L21/762H01L29/78
CPCH01L21/7624H01L21/76832H01L21/76897H01L29/78H01L23/485H01L23/5226H01L23/5283H01L23/528H01L23/53228H01L23/53257H01L23/535
Inventor J·H·张
Owner STMICROELECTRONICS SRL