Bit cycle method for improving dynamic performance of hybrid resistance and capacitance type analog to digital converter

Abstract

The invention discloses a bit cycle method for improving the dynamic performance of a hybrid resistance and capacitance type analog to digital converter. The applied technical field is a high-precision analog to digital converter in the field of microelectronics and solid state electronics. The bit cycle method provided by the invention is applicable to successive approximation analog to digital converter of any structure, the core idea is to split a most significant bit (MSB) capacitance and secondary most significant bit (MSB-capacitance), a capacitance array is divided into four groups, and the capacitance order is changed in each bit cycle to a dynamic averaging effect of capacitance errors is realized. The bit cycle method is characterized in that no correction algorithm needs to be introduced, no correction DAC needs to be introduced, the sampling rate of the analog to digital converter is not sacrificed, and the normal operation of the analog to digital converter is not interrupted. The bit cycle method provided by the invention can be used for carrying out dynamic averaging on the capacitance errors, therefore compared with the traditional correction method that depends on the correction DAC and the correction algorithm to improve the linearity, the structure is simpler, the occupied chip area is smaller, and a on-chip effect is realize more easily.

Description

technical field [0001] The invention relates to a novel successive approximation analog-to-digital converter (SAR ADC) bit cycle method, and the technical field of direct application is a high-precision analog-to-digital converter in the field of microelectronics and solid-state electronics. Background technique [0002] The analog-to-digital converter converts the real-world analog signal into a digital signal. It is a process of filtering, sample-holding and encoding. The analog-to-digital converter has been widely used in various on-chip systems. The requirements of different systems are different, and the performance of the analog-to-digital converter has a great influence on the stability, reliability and durability of the system. [0003] The performance index of the analog-to-digital converter is usually explained from two aspects: static parameters and dynamic parameters. The static parameters mainly include offset (Offset), missing code (Missing Code), monotonicity ...

AI Technical Summary

Problems solved by technology

The disadvantage of analog correction in the foreground is that an additional correction DAC needs to be introduced, and the normal operation of the analog-to-digital converter needs to be interrupted

Background digital calibration usually uses the "Least Mean Square Error" (LMS: Least MeanSquare) algorithm to correct the mismatch of capacitors, and the calibration scheme based on the LMS algorithm has high precision and good calibration effect under the given error modeling conditions. However, if the initial value is not selected properly, it will increase the complexity of the algorithm, and even cause problems such as non-convergence of the algorithm, which is not easy to implement on-chip

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