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Novel BiCMOS sensitive amplifier design

A kind of sensitive amplifier, a new type of technology, used in instruments, static memory, digital memory information and other directions, can solve the problems of slow readout time and high power consumption

Inactive Publication Date: 2017-01-18
马利峰
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

The structure consumes a lot of power and the readout time is slow

Method used

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  • Novel BiCMOS sensitive amplifier design
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Embodiment Construction

[0013] The specific implementation manners of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0014] Sensitive amplifiers in the prior art such as figure 1 As shown, the sensitive amplifying unit is composed of four MOS tubes. If the BL and BLN signals are weakly high and weakly low respectively, the positive feedback of the inverter can pull BL and BLN to strong high and strong low, and the inverter is in transition The region has a large gain, so the output differential signal can be amplified, the structure consumes a lot of power, and the readout time is slow.

[0015] The novel BiCMOS sensitive amplifier structure of the present invention is as figure 2 As shown, the circuit includes a BiCMOS operational amplifier structure: a differential pair composed of two bipolar devices Q1 and Q2, a current mirror composed of two NMOS transistors N10 and N11, a current control transistor N12, and a pre-amplifier composed of...

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PUM

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Abstract

The invention belongs to the technical field of an integrated circuit, and discloses a novel BiCMOS sensitive amplifier design used for an anti-fuse OTP memory, the circuit uses a BiCMOS technology, an op-amp structure is taken as a base, a pre-charging and discharging sequential control mechanism is combined, the programmed anti-fuse with inconsistent impedance states is successfully read to a conduction state, unmistakable reading operation is guaranteed, the read data is real and reliable, memory reliability is increased, the novel BiCMOS sensitive amplifier comprises the op-amp structure, a pre-charging device, three current pathways of CH1, CH2, and CH3, the op-amp structure and the current pathway circuit can successfully detect the programmed anti-fuses with a high impedance connection state and inconsistent connection states to a short circuit state, the novel BiCMOS sensitive amplifier has adjustable and detectable resistance range, the pre-charging device is used for pre-charging the output bit line to high level, so that the read speed is increased, and the precision on the sensitive amplifier is improved.

Description

technical field [0001] The present invention relates to the technical field of integrated circuits, more specifically, the present invention relates to the BiCMOS sensitive amplifier design technology used in the integrated circuit to read out the data in the anti-fuse OTP memory rapidly and stably. [0002] technical background [0003] The sense amplifier is the core component of the memory, and its function is to convert the weak signal on the bit line into an output signal that meets the requirements. The performance of the sense amplifier is greatly related to the overall performance of the semiconductor memory. Sensitive amplifiers in the prior art such as Figure 1 As shown, the four-tube MOS constitutes a sensitive amplification unit. If the BL and BLN signals are weak high and weak low respectively, the positive feedback through the inverter can pull BL and BLN to strong high and strong low. The inverter has a large gain in the transition region, so the output diff...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C7/06
Inventor 马利峰
Owner 马利峰
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