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Method used for eliminating photomask random error induced wafer defective pixels

A random error and photomask technology, applied in the field of semiconductors, can solve problems such as no effective processing, and achieve the effect of low cost and high efficiency

Active Publication Date: 2017-02-01
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, when the dead pixels are caused by random errors in the mask, there is currently no method that can effectively deal with these random dead pixels

Method used

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  • Method used for eliminating photomask random error induced wafer defective pixels
  • Method used for eliminating photomask random error induced wafer defective pixels
  • Method used for eliminating photomask random error induced wafer defective pixels

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Embodiment Construction

[0021] In the following description, numerous specific details are given in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without one or more of these details. In other examples, some technical features known in the art are not described in order to avoid confusion with the present invention.

[0022] It should be understood that the invention can be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0023] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the / the" are intended to include...

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Abstract

The invention provides a method used for eliminating photomask random error induced wafer defective pixels. The method comprises the following steps: determining that the defective pixels of a wafer are induced by photomask random errors; marking photomask areas corresponding areas including the defective pixels, and respectively adopting the photomask areas as a non-exposure area of a first photomask and an only-exposure area of a second photomask; exposing the first photomask except the non-exposure area; and exposing the only-exposure area of the second photomask, wherein the first photomask and the second photomask are made of electroc beams under same conditions, and a pattern on the wafer is generated based on a pattern on the first photomask. The method used for eliminating photomask random error induced wafer defective pixels can effectively eliminate the photomask random error induced wafer defective pixels only through two-stage exposure by adopting two photomasks, so the method has the advantages of low cost and high efficiency.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for eliminating on-wafer weak points caused by random errors in photomasks. Background technique [0002] As the complexity of integrated circuits increases, the feature size becomes smaller and smaller. When the feature size of the integrated circuit is close to the system limit of the exposure of the lithography machine, that is, when the feature size is close to or smaller than the lithography light source, the layout produced on the silicon wafer will be obviously distorted. This phenomenon is called the optical proximity effect. In order to deal with the optical proximity effect, a resolution enhancement technique is proposed. Among them, Optical Proximity Correction (OPC) has become the most important technology. [0003] After the design layout is OPC, a post-OPC layout (post-OPC layout) is formed. A mask writer (mask writer) generates a corresponding mas...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G03F7/20G03F1/36G03F1/72G03F1/84
Inventor 杜杳隽
Owner SEMICON MFG INT (SHANGHAI) CORP