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Wafer and preparation method thereof

A technology of wafers and grains, applied in semiconductor/solid-state device manufacturing, electrical components, electrical solid-state devices, etc., can solve problems such as complex process and high cost, achieve simplified process flow, reduce production cost, and have a wide range of applications Effect

Inactive Publication Date: 2017-02-15
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

But the process is very complex and expensive

Method used

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  • Wafer and preparation method thereof
  • Wafer and preparation method thereof
  • Wafer and preparation method thereof

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Experimental program
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Effect test

Embodiment 1

[0040] Such as figure 1 As shown, a wafer 1 includes a plurality of crystal grains 2 with the same structure, and the superjunction cell structure in the middle of each crystal grain 2 includes a P-type doped region 3 and an N-type doped region 4, such as Figure 2(a) , 2(b) As shown, the P-type doped region 3 is divided into P-type sub-regions 31, 32, ..., 3n, ..., and the N-type doped region 4 is divided into N-type sub-regions 41, 42, ..., 4n, .... The heterogeneous sub-regions are strip-shaped, and the two sub-regions are alternately arranged in a row, and the adjacent P-type sub-regions 31, 32, ..., 3n, ... are respectively divided into N-type sub-regions 41, 42, ..., 4n, ... separated.

[0041] The preparation method of above-mentioned wafer, comprises the following steps:

[0042] (1) N-type silicon wafers are used as material A, and P-type silicon wafers are used as material B;

[0043] (2) The front side of material B is implanted with hydrogen ions;

[0044] (3)...

Embodiment 2

[0049] A wafer 1 includes a plurality of crystal grains 2 with the same structure, and the superjunction cell structure in the middle of each crystal grain 2 includes a P-type doped region 3 and an N-type doped region 4, such as Figure 3(a) , 3(b) As shown, the P-type doped region 3 is divided into P-type sub-regions 31, 32, ..., 3n, ..., each P-type sub-region is square and arranged in multiple rows and columns and aligned with each other, and each adjacent P-type sub-region The regions are separated by N-type doped regions 4, that is, on the same row, there are N-type doped regions 4 between adjacent P-type sub-regions; on the same column, adjacent P-type sub-regions are separated by The N-type doped regions 4 are separated.

[0050] The preparation method of above-mentioned wafer, comprises the following steps:

[0051] (1) N-type silicon wafers are used as material A, and P-type silicon wafers are used as material B;

[0052] (2) The front of material A and material B ...

Embodiment 3

[0060] A wafer 1 includes a plurality of crystal grains 2 with the same structure, and the superjunction cell structure in the middle of each crystal grain 2 includes a P-type doped region 3 and an N-type doped region 4, such as Figure 4(a) , 4(b) As shown, the P-type doped region 3 is divided into P-type sub-regions 31, 32, ..., 3n, ..., each P-type sub-region is square and arranged in multiple rows and columns, and each adjacent P-type sub-region is covered by N Type doped regions 4 are separated, that is, on the same row, there are N-type doped regions 4 between adjacent P-type sub-regions; the difference from embodiment 2 is that the adjacent upper and lower rows are staggered by a certain distance, and the interlaced rows are Aligned in the column direction, adjacent P-type sub-regions in the same column are separated by N-type doped regions 4 .

[0061] The preparation method of above-mentioned wafer, comprises the following steps:

[0062] (1) N-type silicon wafers a...

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Abstract

The invention provides a wafer and a preparation method thereof. The wafer comprises multiple grains with a same structure. The super junction cellular structure in the middle of each of the grains comprises a P type doping area and an N type doping area. At least one doping area is divided into multiple sub areas. The adjacent sub areas with the same doping type are separated by a doping area with another type. The preparation method comprises the steps of (1) making a material A by using an N type silicon piece, and making a material B by using a P type silicon piece, (2) injecting hydrogen ions into the front side of the material B, (3) making a groove in the material A according to a pattern, and making a groove in the material B according to an opposite pattern, (4) connecting the material A with the groove and the material B with the groove to form a semiconductor C, (5) stripping the bottom of the material B for repeated use, and (6) carrying out wafer surface processing. According to the wafer and the preparation method, the multiple times of injection and multilayer epitaxial are not needed, the process flow is simplified, thus the production cost is reduced, a P-N bar with an ultra high aspect ratio can be formed by the water, and the application range of the wafer is wide.

Description

technical field [0001] The invention belongs to the technical field of semiconductors, and in particular relates to a wafer and a preparation method thereof. Background technique [0002] Super Junction (Super Junction) technology is to replace the traditional drift region with multiple alternating P-N strips. In the on state, the current flows through the highly doped P / N type region, so that the on resistance becomes smaller; state, alternating P-N mutual compensation provides a high breakdown voltage. Therefore, the chip performance can be significantly improved and the chip area can be reduced. Since it was proposed, many scholars have conducted in-depth research on this structure and invented super-junction devices such as super-junction MOS and super-junction IGBT. The realization of the super junction structure generally adopts the scheme of multiple implantation and multi-layer epitaxy to form the super junction. But the process is very complex and expensive. Co...

Claims

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Application Information

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IPC IPC(8): H01L21/82H01L27/02
CPCH01L27/0207H01L21/82
Inventor 乔明方冬章文通张波
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA