Scheduling method of hardware accelerators in C-RAN

A technology of hardware accelerator and scheduling method, which is applied in the directions of instruments, electrical components, program startup/switching, etc. It can solve the problems of consuming signal processing time, high computational complexity, and CPU processing resources occupied by computationally intensive modules, and achieves increased System throughput, high system throughput rate, and the effect of improving signal processing speed

Active Publication Date: 2017-04-19
TONGJI UNIV
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Problems solved by technology

[0003] Computation-intensive modules in C-RAN occupy CPU processing resources and consume most of the signal processing time. They are the key to improving signal processing speed
In order to improve the throughput rate of the C-RAN system, reduce the time loss caused by this part of the operation, and meet the requirements of the C-RAN for real-time processing of wireless signals, we use FPGA (Field-Programmable GateArray) as a hardware accelerator to implement these computationally complex tasks. module

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  • Scheduling method of hardware accelerators in C-RAN
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  • Scheduling method of hardware accelerators in C-RAN

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Embodiment Construction

[0034] The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments. This embodiment is carried out on the premise of the technical solution of the present invention, and detailed implementation and specific operation process are given, but the protection scope of the present invention is not limited to the following embodiments.

[0035] The system overall structure of the dispatching method of hardware accelerator in a kind of C-RAN is as follows figure 1 Shown:

[0036] Run the LTE base station physical layer program (LET PHY) in the virtual machine; the modules with high computational complexity are implemented with hardware accelerators, and multiple hardware accelerator devices are connected to the server through PCIe (PCI-Express is the latest bus and interface standard) The host installs the device driver, and the server calls the device driver to communicate with the device;

[0037] Install Xen, modi...

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Abstract

The invention relates to a scheduling method of hardware accelerators in a C-RAN. The method comprises the following steps of 1) establishing a task queue work_queue in a virtual machine controller Dom0, and simultaneously, aiming at each hardware accelerator, establishing a task queue write_queue and a task queue read_queue; 2) after the virtual machine controller Dom0 receives a request of a virtual machine DomU, adding the request in the task queue work_queue according to a first-come-first-served policy; 3) successively taking out tasks in the task queue work_queue, selecting the hardware accelerator with a current minimum load, and putting the task which is taken out into the corresponding task queue to complete a scheduling design of the plurality of hardware accelerators so that a virtual machine shares the accelerators. A signal processing speed is increased, hardware accelerator loads are balanced and a system throughput is increased.

Description

technical field [0001] The invention relates to the technical field of virtualization and network communication, in particular to a scheduling method of a hardware accelerator in a C-RAN. Background technique [0002] C-RAN is a clean system based on Centralized Processing, Collaborative Radio and Real-time Cloud Infrastructure. Its essence is to achieve low cost, high bandwidth and flexible operation by reducing the number of base station equipment rooms, reducing energy consumption, adopting collaborative and virtualization technologies, realizing resource sharing and dynamic scheduling, and improving spectrum efficiency. [0003] Computing-intensive modules in C-RAN occupy CPU processing resources and consume most of the signal processing time. They are the key to improving the signal processing speed. In order to improve the throughput rate of the C-RAN system, reduce the time loss caused by this part of the operation, and meet the requirements of the C-RAN for real-tim...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04W28/08H04W28/14G06F9/48G06F9/50
CPCG06F9/4881G06F9/5011G06F9/5083H04W28/08H04W28/14
Inventor 吴俊王睿朱慧汤绍先吴坤恒刘典
Owner TONGJI UNIV
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