Architecture and method for efficient testing of slow peripherals based on software self-testing technology

Abstract

The invention discloses a slow peripheral high-efficiency test framework and method based on software self-test technology, and belongs to the technical field of processor test. The invention uses a pseudo-random number generation program to simulate a linear feedback shift register to generate test patterns that meet the requirements of various slow tests, eliminates the need for additional specific test hardware circuits, can flexibly configure primitive polynomials, and uses the microprocessor's own instructions Complete the generation and application of test patterns, and arrange the test sequence of each slow peripheral test group according to the long-wait test group priority test principle, so that the total test time of multiple peripherals can be reduced as much as possible, and the idle utilization of the processor can be improved. Rate.

Description

technical field [0001] The invention discloses a slow-speed peripheral high-efficiency testing framework and method based on a software self-testing technology for circuits, and belongs to the technical field of processor testing. Background technique [0002] The testing of slow peripherals is one of the research directions of processor system testing. The clock frequency of the slow peripherals is much lower than the processor clock frequency, causing the processor to idle for a long time while testing the slow peripherals. [0003] Existing slow peripherals (such as: UART, I 2 The clock frequency of C, SPI) is much lower than the clock frequency of the processor, for example, the clock of the processor is 100M, and the peripheral clock is only 10M, 20M, or even lower. At the same time, due to the serial data transmission method, the above reasons lead to a long waiting time for data transmission between the processor and such peripherals, which seriously limits the high...

AI Technical Summary

Problems solved by technology

[0005] The purpose of the present invention is to address the deficiencies of the above-mentioned background technology, to provide a slow peripheral efficient test framework and method based on software self-test technology, without additional pseudo-random number generator circuits, and to use test scheduling algorithms reasonably and efficiently. Realize the test of slow peripherals, and solve the technical problems of high power consumption and poor scalability of existing slow peripheral tests

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