Preparation method of large-size III-V heterogeneous substrate

A heterogeneous substrate, III-V technology, applied in chemical instruments and methods, semiconductor/solid-state device manufacturing, diffusion/doping, etc., can solve the problems of high cost, high process difficulty, low efficiency, etc. cost, guaranteed material performance, and the effect of improving integration and design flexibility

Inactive Publication Date: 2017-05-10
SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
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  • Abstract
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  • Claims
  • Application Information

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Problems solved by technology

[0004] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a method for preparing a large-size III-V heterogeneous substrate, which is used to solve the process difficulty in preparing a large-size III-V heterogeneous substrate in the prior art Large, inefficient, and costly problems

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  • Preparation method of large-size III-V heterogeneous substrate
  • Preparation method of large-size III-V heterogeneous substrate
  • Preparation method of large-size III-V heterogeneous substrate

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Embodiment Construction

[0032] Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

[0033] see Figure 1 to Figure 15 . It should be noted that the diagrams provided in this embodiment are only schematically illustrating the basic idea of ​​the present invention, so that only the components related to the present invention are shown in the diagrams rather than the number, shape and Dimensional drawing, the type, quantity and proportion of each component can be changed arbitrarily during actual implementation, and th...

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Abstract

The invention provides a preparation method of a large-size III-V heterogeneous substrate. The preparation method comprises the following steps that S1) a III-V epitaxial structure which includes an injection surface is provided; S2) ion implantation is carried out on the injection surface, and a defect layer is formed in a position of a preset depth of the III-V epitaxial structure; S3) a support substrate is provided, and the injection surface is bonded to the support substrate; and S4) part of the III-V epitaxial structure is peeled along the defect layer, so that part of the III-V epitaxial structure is transferred on the support substrate to form an III-V film on the support substrate, and the III-V heterogeneous substrate is obtained. The preparation method of the large-size III-V heterogeneous substrate can be used to solve the problems that preparation of the large-size III-V heterogeneous substrate in the prior art is high in technical difficulty, low in efficiency and high in cost.

Description

technical field [0001] The invention belongs to the technical field of semiconductor preparation, and in particular relates to a method for preparing a large-size III-V heterogeneous substrate using ion implantation stripping technology combined with epitaxial growth technology. Background technique [0002] Microelectronic technology based on silicon-based CMOS (Complementary Metal Oxide Semiconductor) integrated circuits has experienced rapid development for more than half a century along "Moore's Law". After entering the 14nm technology node, the development of microelectronics technology will no longer follow the law of proportional reduction, but will turn to the post-Moore era of integration with non-silicon-based CMOS devices, non-digital functional devices, and non-CMOS working mode devices. develop. Compared with silicon materials, group III-V semiconductor materials have higher carrier mobility, and at the same time, group III-V semiconductor materials with direct...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/18C30B31/22C30B33/02
CPCC30B31/22C30B33/02H01L21/187
Inventor 欧欣龚谦游天桂黄凯林家杰张润春
Owner SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
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