Multi-station rapid configuration device and configuration method thereof for FPGA test

Abstract

The invention provides a multi-station rapid configuration device and a configuration method thereof for FPGA test. A test module sends an operation instruction to a configuration module, realizes selection of operation stations, selection of configuration readback operation type and selection of configuration mode, and receives an operation result returned by the configuration module; the configuration module receives an operation instruction of the test module, and sends the operation instruction to a configuration adapter; and the configuration adapter, according to the operation instruction, finishes configuration of an FPGA chip to be tested and readback of configuration data and sends the readback data to the test module. The multi-station rapid configuration device and method realize configuration operation of a plurality of FPGA chips to be tested simultaneously, and realize readback operation of the configuration data, support selection of multiple configuration modes, are compatible with a plurality of test platforms, and realize isolation protection and dynamic level matching of the configuration adapter and the FPGA chip to be tested; the configuration adapter does not occupy test program vector and channel resources during working, thereby saving storage medium, and simplifying hardware design; and configuration data is flexible to update, and configuration time is saved.

Description

technical field [0001] The invention relates to a multi-station rapid configuration device for FPGA testing and a configuration method thereof. Background technique [0002] FPGA (Field-Programmable Gate Array) emerged as a semi-custom circuit in the field of application-specific integrated circuits. The disadvantage of limited number of circuits can be widely used in aerospace, communications, computer hardware systems, program control, digital systems and other fields. FPGA can quickly configure a general-purpose integrated circuit into a dedicated digital circuit required by users through programming, thus greatly speeding up the research and development cycle of electronic products, reducing research and development costs, and shortening the time to market. [0003] With the widespread application of FPGAs, the requirements for device reliability are getting higher and higher. At the same time, because the integration level of FPGAs is getting higher and higher, and the...

AI Technical Summary

Problems solved by technology

The patented "FPGA multiple real-time reconfiguration adapter based on test system" has a large hardware overhead. When testing a tens of millions of FPGA chips, thousands of different configuration data need to be downloaded, and the storage of configuration data requires a large amount of storage. Space and hardware overhead are large; the update of configuration data in the test program debugging stage is relatively complicated, and it is necessary to connect the EDA development support board to update the configuration data to the memory array. At the same time, it is necessary to control the configuration of the FPGA chip through test vectors during configuration. Occupies already tight test system resources; at the same time, this solution only implements the configuration of the FPGA chip. During the test process, it is often necessary to read back the loaded configuration data to test the configuration circuit. This solution cannot realize the configuration of the configuration data. readback of

A well-designed FPGA chip can often support multiple configuration modes, and this solution cannot switch between different configuration modes.

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