Multicomputer system time synchronization method based on VPX framework and device

A system time and multi-computer technology, applied to TV system components, generating/distributing signals, instruments, etc., to achieve obvious economic benefits

Inactive Publication Date: 2017-05-24
CHINA SHIP DEV & DESIGN CENT
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  • Description
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Problems solved by technology

The original B-code time synchronization method (using a single B-code board) is no longer applicable. In order to solve this problem, a time synchronization method based on blade server is designed and proposed.

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  • Multicomputer system time synchronization method based on VPX framework and device
  • Multicomputer system time synchronization method based on VPX framework and device
  • Multicomputer system time synchronization method based on VPX framework and device

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Embodiment Construction

[0029] In order to make the object, technical solution and advantages of the present invention more clear, the present invention will be further described in detail below in conjunction with the examples. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0030] The B code circuit adopted in the present invention mainly includes a processor (P2020), a level conversion circuit, an FPGA circuit, a PCIE switch, and an SRIO switch. Among them, the P2020 processor mainly runs the software program on the board, configures PCIE switching, SRIO switching and some management functions; the level conversion circuit completes the level conversion from RS485 / 422 to TTL signal; FPGA realizes the analysis and timing of B code information, It also provides PCIE interface and SRIO interface for the blade motherboard to access at any time.

[0031] The PCIE switch completes the PCIE network...

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Abstract

The invention discloses a multicomputer system time synchronization method based on VPX framework and device. The device comprises an electrical level conversion circuit for converting electrical level from input B code fulfills RS485 / 422 to TTL signal; a FPGA circuit for solving input B code to year-month-day-hour-minute-second message and recovering pulse per second message; analysis and punctuality of B code message is achieved; a time service register block for clock count through receiving temperature-compensation crystal oscillator and reset handle from the pulse per second message , the time information of resolution ratio over one microsecond is achieved; a PCIE exchanger for decoding the time information from a FPGA circuit provided by a blade sever; the PCIE exchanger is connected with the FPGA circuit through a PCIE port provided by the FPGA circuit; a processor for disposing PCIE exchange message, the processor is connected with the PCIE exchanger. According to the method and the device, the time precison can be reached within 10 us, the matter of unification of time of blades on the blade sever can be solved effectively, economic benefit is obvious.

Description

technical field [0001] The invention relates to time synchronization technology, in particular to a multi-computer system time synchronization method and device based on VPX architecture. Background technique [0002] Time synchronization is one of the basic requirements of electronic information systems, especially in high-performance computing, military industry, telecommunications and other fields. At present, there are many methods of time synchronization, such as pulse synchronization, serial port information synchronization, IRIG-B code information synchronization, etc., each of which has advantages and disadvantages. The IRIG-B code, as an internationally accepted time code, is widely used because of its precise time synchronization, simplifies the time synchronization loop, and contains complete absolute time scale information. However, the current IRIG-B time synchronization method is mainly used in a stand-alone mode, that is, a machine is installed with a B code ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F1/12
CPCG06F1/12G02F1/133308H04N5/64G02F1/133305G02F1/133314G02F1/133514G02F1/133602
Inventor 罗威李寒雨王逸群肖俊东李家志
Owner CHINA SHIP DEV & DESIGN CENT
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