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Method and device for testing FPGA interconnection line

A test method and interconnection line technology, applied in the field of FPGA test, can solve problems such as low efficiency, achieve the effect of simplifying test operation and improving test efficiency

Active Publication Date: 2017-06-13
SHENZHEN STATE MICROELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The main technical problem to be solved by the present invention is to provide a method and device for testing FPGA interconnection lines to solve the problem of low efficiency in testing FPGA interconnection lines based on the layer decomposition model

Method used

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  • Method and device for testing FPGA interconnection line
  • Method and device for testing FPGA interconnection line
  • Method and device for testing FPGA interconnection line

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0053] see figure 2 As shown, the FPGA interconnection testing method provided in this embodiment includes:

[0054] S201: Obtain the horizontal interconnection lines to be tested and the vertical interconnection lines to be tested outside the switch matrix to be tested of the FPGA device.

[0055] In this embodiment, different types of interconnection lines to be tested can be tested separately, and the test method in this embodiment is applicable to any type of interconnection line test; the horizontal interconnection line to be tested in this embodiment refers to The interconnection lines to be tested on the upper and lower sides of the switch matrix; the vertical interconnection lines refer to the interconnection lines to be tested on the left and right sides of the switch matrix.

[0056] S202: Obtaining a horizontal interconnection line to be tested and a vertical interconnection line to be tested are respectively modeled to generate an interconnection line test patter...

Embodiment 2

[0091] The present embodiment provides a kind of FPGA interconnection testing device, see Figure 4 shown, including:

[0092] The interconnection line acquisition module 41 is used to obtain the horizontal interconnection line to be tested and the vertical interconnection line to be tested outside the switch matrix to be tested of the FPGA device; , the interconnection lines to be tested on the lower two sides; the vertical interconnection lines refer to the interconnection lines to be tested on the left and right sides of the switch matrix.

[0093] The test pattern generation module 42 is used to model the horizontal interconnection line to be tested and the vertical interconnection line to be tested respectively to generate an interconnection line test pattern. The test pattern generation module 42 models the horizontal interconnection line to be tested and the vertical interconnection line to be tested respectively, that is, models the horizontal interconnection line to ...

Embodiment 3

[0110] This embodiment proposes that the vertical and horizontal decomposition model of the FPGA interconnection is universal, and does not target any FPGA device, and does not require a special unit structure, as long as the design of the interconnection satisfies the distribution in the vertical and horizontal directions. Currently, any FPGA device on the market has a two-wire structure. Therefore, for ease of understanding, this embodiment uses a representative two-wire structure as an example to illustrate the vertical and horizontal decomposition model of interconnection lines. Such as Figure 5-1 and Figure 5-2 As shown, the longitudinal two-long line and the horizontal two-long line are modeled separately. Figure 5-1 and Figure 5-2 In , the vertical and horizontal decomposition wiring model is an abstraction of the physical connection of the internal interconnection lines of the FPGA device. Regardless of whether it is a horizontal interconnection line or a vertic...

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Abstract

The invention discloses a method and a device for testing FPGA interconnection lines. The transverse interconnection lines to be measured and the longitudinal interconnection lines to be measured outside a switch matrix to be measured of an FPGA device are obtained, and then the acquired transverse interconnection lines to be measured and longitudinal interconnection lines to be measured are modeled in both horizontal and vertical directions to generate a test pattern of the interconnection lines, which is converted into a test bit stream file and then the file is input to the switch matrix to be tested. The method and the device for testing FPGA interconnection lines disconnect the interconnection lines in both transverse and longitudinal directions, and each becomes a net type separately. When generating the interconnect test pattern, the interconnection lines are only required to be dichotomous in the vertical and horizontal directions. A vertical and horizontal decomposition model in application processing is much easier than a layer decomposition, and various types of interconnection lines are only required to be dichotomous, therefore the test operation can be simplified and the testing efficiency can be improved to a great extent.

Description

technical field [0001] The invention relates to the field of FPGA (Field-Programmable Gate Array, ie Field Programmable Gate Array) testing, in particular to an FPGA interconnection line testing method and device. Background technique [0002] Programmable interconnects are a vital part of the resources in FPGA devices. The FPGA device connects the programmable resources and clock control resources inside the device as a whole through interconnection lines. There are programmable switch arrays between the interconnection lines. These programmable switch arrays enable the interconnection lines inside the FPGA device to be connected and insulated from line to line according to the user's designation, so as to realize the design. Features. [0003] The integrity of the interconnection is the basis for the testability of the internal resources of the entire FPGA device. Faults in any of the interconnect lines may cause the configuration of the circuit design to fail. In orde...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/02G06F17/50
CPCG01R31/50G06F30/34
Inventor 何东东蔡广全温长清包朝伟
Owner SHENZHEN STATE MICROELECTRONICS CO LTD
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