Manufacturing method of groove-type double grid MOS structure

Abstract

The invention discloses a manufacturing method of a groove-type double grid MOS structure. The method comprises steps of 1) forming grooves in a silicon substrate by etching; 2) growing a groove layer joint film in the grooves; 3) growing polycrystalline silicon in the grooves, and performing reverse etching to form source polycrystalline silicon; 4) removing a part of the groove layer joint film, and enabling the height of the groove layer joint film to be lower than that of the source polycrystalline silicon; 5) growing a thin oxide layer of the thickness of 200-400 Angstrom; 6) depositing silicon nitride; 7) growing grid polycrystalline silicon and performing reverse etching to the substrate surface; and 8) performing base injection and source injection, depositing an inter-layer dielectric layer, etching contact holes, manufacturing metal and passivation layers and finishing manufacturing of the device. The method improves the quality of the gate oxide and the pressure-resistance property and the reliability of the device by optimizing the membranous structure of the gate oxide and the dielectric layer and through the combination of the thin gate oxygen + silicon nitride, thereby satisfying the leakage requirements between the two layers of polycrystalline silicon.

Description

technical field [0001] The invention relates to the field of integrated circuit manufacturing, in particular to a manufacturing method of a trench type double-layer gate MOS structure. Background technique [0002] The structure and morphology of the existing trench-type double-layer gate MOS devices are as follows: figure 1 , 2 As shown, the lower layer of the trench is the source polysilicon, the upper layer is the gate polysilicon, the sidewall of the trench is a trench layer junction film (TCH liner), and between the gate polysilicon and the source polysilicon is a gate oxide and an IPO dielectric layer (trench The portion of the trench sidewall in contact with the gate polysilicon is the gate oxide). [0003] Among them, the gate oxide between the gate polysilicon and the source polysilicon and the IPO dielectric layer (inter-polysiliconoxide, the oxide layer between polysilicon, which is formed by oxidizing the source polysilicon) are formed on silicon and polysilico...

AI Technical Summary

Problems solved by technology

The advantage of this process method is that the process is simple, and the disadvantage is that it uses a wet oxygen oxidation method, the quality of the gate oxide is not good enough, and there is a control voltage (V RAMP ) and reliability (Reliability) hidden dangers, easy leakage between two layers of polysilicon

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