Semiconductor layout structure

Abstract

The invention discloses a semiconductor layout structure. The semiconductor layout structure comprises at least one first signal line and a pair of low-power supply potential lines, wherein the first signal line and the low-power supply potential lines extend along a first direction, the low-power supply potential lines are arranged along a second direction, the first direction and the second direction are perpendicular to each other, and more importantly, the low-supply potential lines are formed at two opposite sides of the first signal line.

Description

technical field [0001] The present invention relates to a semiconductor layout structure, in particular to a semiconductor layout structure that can be completed by using multiple patterning in a semiconductor back-end-of-line (BEOL) process. Background technique [0002] In the manufacturing process of semiconductor integrated circuits, the manufacture of the microstructure of integrated circuits requires the use of photolithography in appropriate substrates or material layers such as semiconductor substrates / film layers, dielectric material layers, or metal material layers. And etching and other manufacturing processes to form tiny patterns with precise dimensions. To achieve this goal, the existing semiconductor technology forms a mask layer (mask layer) on a target material layer, so that these tiny patterns are formed / defined in the mask layer, and then the patterns are transferred to the target film layer . In general, the mask layer may include a patterned photoresi...

AI Technical Summary

Problems solved by technology

It can be seen that the multi-patterning method is a precise manufacturing process that requires extremely high manufacturing process control, so the adoption of the multi-patterning method inevitably increases the complexity and cost of the manufacturing process.

Images