Semiconductor devices and inverter having the same

Abstract

Disclosed are CMOS device and CMOS inverter. The CMOS device includes a substrate having active lines extending in a first direction and defined by a device isolation layer, the substrate being divided into an NMOS area, a PMOS area and a boundary area interposed between the NMOPS and the PMOS areas and having the device isolation layer without the active line, a gate line extending in a second direction across the active lines and having a first gate structure on the active line in the first area, a second gate structure on the active line in the second and a third gate structure on the device isolation layer in the third area. The electrical resistance and parasitic capacitance of the third gate structure are smaller than those of the NMOS and the PMOS gate structures. Accordingly, better AC and DC performance of the CMOS device can be obtained.

Description

[0001] Cross References to Related Applications [0002] This application claims priority from Korean Patent Application No. 10-2015-0141584 filed with the Korean Intellectual Property Office on October 8, 2015, the entire contents of which are incorporated herein by reference. technical field [0003] The present application generally relates to a semiconductor device and an inverter having the semiconductor device, and more particularly relates to a complementary metal oxide semiconductor (CMOS) having a p-type MOS (PMOS) device and an n-type MOS (NMOS) device. CMOS) device and a CMOS inverter with the CMOS device. Background technique [0004] Due to recent high integration and miniaturization of memory devices, the size of an active region in a semiconductor substrate is reduced. Reductions in gate width and channel length in cell transistors lead to increases in gate resistance and threshold voltage. Specifically, a decrease in channel length in metal-oxide-semiconduc...

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Problems solved by technology

[0006] In addition to the aforementioned short-channel effects and current leakage, reducing the size of memory devices also leads to increases in parasitic capacitance and resistance

Specifically, when the line width of the gate electrode decreases to tens of nanometers and the area occupied by the gate electrode finally decreases, the parasitic capacitance of the CMOS device finally increases at the boundary region between PMOS and NMOS, thereby significantly reducing the CMOS Alternating Current (AC) Performance of the Device

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