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Three-dimensional chip with fault repairing device and fault repairing and data reading method

A three-dimensional chip, fault repair technology, applied in static memory, instruments, etc., can solve the problems of increasing chip production cost, waste of redundant resources, multiple redundant resources, etc., to improve the utilization rate of redundant resources, improve the yield, The effect of reducing production costs

Active Publication Date: 2017-08-18
SHANGHAI JIAO TONG UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a three-dimensional chip with a fault repair device and a fault repair and data reading method, which is used to solve the need to arrange more redundancy in the existing repair methods. resources, resulting in a waste of redundant resources and increasing the production cost of the chip

Method used

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  • Three-dimensional chip with fault repairing device and fault repairing and data reading method
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  • Three-dimensional chip with fault repairing device and fault repairing and data reading method

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Experimental program
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Embodiment 1

[0085] Such as figure 1 As shown, this embodiment provides a fault repair method for a three-dimensional chip, and the fault repair method includes:

[0086] 1) Obtain the address information of the wrong unit in each layer of wafer through testing;

[0087] 2) dividing the three-dimensional chip into a mapping layer and a mapped layer, and using an error aggregation algorithm to gather error units in the mapping layer to the mapped layer;

[0088] 3) Redundantly repair the error units in the mapped layer through global redundant resources.

[0089] Specifically, in 1), the method for obtaining the address information of the error cell in each layer of wafers by testing includes:

[0090] 1.1) Read the data of any storage unit in any layer of the chip, if the reading is successful, then skip to 1.2); if the reading fails, the storage unit is an error unit;

[0091] 1.2) Compare the read data in the storage unit with its corresponding reference data; if they are the same, th...

Embodiment 2

[0106] Such as figure 2 As shown, the present embodiment provides a fault repairing device 15 for a three-dimensional chip, and the fault repairing device 15 includes:

[0107] The test module 151 is used to test the storage units of each layer of wafers to obtain the address information of the error cells in each layer of wafers;

[0108] The error aggregation module 152 is connected to the test module 151, and is used to divide the three-dimensional chip into a mapping layer and a mapped layer, and uses an error aggregation algorithm to gather error units in the mapping layer to the mapped layer; and

[0109] The global redundancy module 153, connected to the error aggregation module 152, is used to store global redundancy resources, and perform redundancy repair on error units in the mapped layer through the global redundancy resources.

[0110] Specifically, the test module 151 includes:

[0111] Data reading module 1511, used to read the data of any storage unit in any...

Embodiment 3

[0136] Such as Figure 6 As shown, this embodiment provides a three-dimensional chip, and the three-dimensional chip includes:

[0137] At least two layers of chips 11 connected by through-silicon vias, wherein each layer of chips further includes a row decoder 12 and a column decoder 13 connected to the chips 11;

[0138] A layer decoder 14 located at the bottom layer of the three-dimensional chip and connected to the row decoder 12 and the column decoder 13 of each layer;

[0139] The failure recovery device 15 as described in the third embodiment connected to the layer decoder 14; and

[0140] A merging module 16 connected to the fault repairing device 15 and each layer of wafers 11 respectively.

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Abstract

The invention provides a three-dimensional chip with a fault repairing device and a fault repairing and data reading method. The fault repairing method includes the steps of firstly, testing to obtain the address information of the faulted unit in the wafer of each layer; secondly, dividing the three-dimensional chip into a mapping layer and a mapped layer, and using a fault aggregation algorithm to aggregate the faulted units in the mapping layer to the mapped layer; thirdly, using global redundant resources to performing redundant repairing on the faulted units in the mapped layer. By the three-dimensional chip with the fault repairing device and the fault repairing and data reading method, the problems that many redundant resources need to be arranged in an existing repairing method, redundant resource waste is caused, and chip production cost is increased are solved.

Description

technical field [0001] The invention belongs to the technical field of semiconductor chips, and in particular relates to a three-dimensional chip with a fault repairing device and a fault repairing and data reading method. Background technique [0002] People always have endless demands for more functions and stronger performance electronic products. In order to meet these demands, the semiconductor industry follows Moore’s Law, continuously reducing the size of transistors and increasing chip integration. can last for 10 years, but the enormous costs associated with it have motivated us to actively explore and deploy alternative integration approaches, which we call "More-than-Moore" integration; the most promising of these One alternative is the three-dimensional integrated circuit chip (3D-IC). [0003] 3D-IC stacks unpackaged bare chips in the vertical direction and packages them into a complete chip. These stacked chips pass signals to each other through a technology c...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C29/44
CPCG11C29/4401G11C2029/4402
Inventor 韩焱李天健蒋力
Owner SHANGHAI JIAO TONG UNIV