Fast security hardware structure of AES algorithm

A hardware structure, fast technology, applied in the field of information security, to achieve the effect of high side channel security and optimized efficiency

Active Publication Date: 2017-08-18
INST OF INFORMATION ENG CAS
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Although the calculation speed of this implementation method is not

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  • Fast security hardware structure of AES algorithm
  • Fast security hardware structure of AES algorithm
  • Fast security hardware structure of AES algorithm

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Embodiment Construction

[0053] The specific technology of the present invention, especially the S-box solution of the mask byte replacement part of the core part will be further described in detail below in conjunction with the accompanying drawings. The S-box solution process of AES is as follows: figure 2 As shown, starting from the input, it includes isomorphic mapping, tower field inversion, inverse isomorphic mapping, affine transformation and output process. In the process of inverting the tower field, the image 3 , Figure 4 and Figure 5 Mask implementation of AND gate, OR gate or NOT gate in . for image 3 The implementation of the symbol AND Masked Gate is abbreviated as (&M), for Figure 4 Use the symbol XOR Masked Gate to express the abbreviation as (∪M), for Figure 5 It is abbreviated as (!M) with the symbol NOT Masked Gate.

[0054] 1. Isomorphic mapping

[0055] The isomorphic map f is a matrix transformation of 8 rows and 8 columns. It does not contain nonlinear AND gates, ...

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Abstract

The invention discloses a fast security hardware structure of an AES algorithm. The fast security hardware structure comprises a secret key extension module and an encryption module; an initial secret key adding module in the encryption module generates initial input to send to a two-out-four selector; a mask byte replacing module preforms mask byte replacement on sharing factors, and then respectively outputs the sharing factors after the mask byte replacement to a line shifting module; the line shifting module inputs a shifting processing result to a line mixing module; the line shifting module and the connected line mixing module send the processing result to a one-out-two selector; the output end of the one-out-two selector is connected with the input end of a round secret key adding module, and the other input end of the round secret key module is connected with the round secret key output end of the secret extension module; the round output end is connected with the round input end of one two-out-four selector; and the round output end of another one-out-two selector is connected with the round input end of the two-out-four selector; ciphertext output ends of two one-out-two selectors are respectively connected with the input end of a ciphertext generating unit. By use of the security hardware structure disclosed by the invention, the security of the sensitive data can be guaranteed.

Description

technical field [0001] The invention proposes a fast and secure hardware structure of the AES algorithm, and the method is resistant to first-order side channel attacks. Hardware designers can use this method to efficiently and safely implement the AES algorithm, resist first-order CPA and DPA attacks, and ensure the security of sensitive data. It belongs to the field of information security technology and is mainly used to ensure the side channel security of encrypted hardware. Background technique [0002] The encryption module is an essential part in systems such as secure communication, authentication, and electronic signature. With the rapid development of Internet of Things applications, encryption modules must be embedded in micro-devices or embedded systems. Therefore, it is of great significance to ensure the efficiency of encryption modules. At the same time, hardware encryption devices are seriously threatened by side-channel attacks, and the direct implementati...

Claims

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Application Information

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IPC IPC(8): H04L9/00H04L9/06H04L9/08
Inventor 张锐张倩周永彬邱爽
Owner INST OF INFORMATION ENG CAS
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