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Apparatus and method for managing breakdown of eeprom memory access transistors

A memory and memory cell technology, applied in the field of memory, can solve the problems of inappropriate consumption, limited increase in duration of erasing and programming high-voltage pulse applications, unacceptable number of programming times, etc., and achieve the effect of avoiding breakdown and leakage

Active Publication Date: 2020-08-21
STMICROELECTRONICS (ROUSSET) SAS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0010] There is a limit to increasing the duration of the application of erase and program high voltage pulses as this would result in unacceptable program cycles
[0011] Alternative solutions have been conceived, such as for example what is known as a "split-voltage" architecture (according to the term commonly used by those skilled in the art), but generally require complex peripheral circuitry and are notably less suitable for dissipating very little Small memory boards such as those used in radio frequency identification ("RFID") tags or in stand-alone memory

Method used

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  • Apparatus and method for managing breakdown of eeprom memory access transistors
  • Apparatus and method for managing breakdown of eeprom memory access transistors
  • Apparatus and method for managing breakdown of eeprom memory access transistors

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Embodiment Construction

[0036] exist figure 1 In , reference numeral DISP denotes an example of an EEPROM type memory device according to the present invention.

[0037] This means DISP comprises a memory plate PM of memory cells CEL, as well as programming means MPR and erasing means MEF notably comprising means HV allowing high programming or erasing voltages to be applied, row and column decoders DECY and DECX and comprising Read device for read amplifier AMPL.

[0038] The row decoder DECY and the column decoder DECX are notably controlled by the programming means MPR and the erasing means MEF and are configured to pass through word lines and control lines WL / CGL respectively and via bit lines BL, for example by means of control blocks. A signal is sent to select a memory cell.

[0039] The means DIS also comprise control means MCM comprising, for example, logic means capable of implementing notably the conventional structure of the respective programming means MPR, erasing means MEF and readi...

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Abstract

A non-volatile electrically erasable and programmable memory type memory device is provided, comprising, a matrix memory plate (PM) of memory cells (CEL) connected to bit lines (BL), configured to select the memory cells (CEL) and apply a programming pulse (VSBL) to the programming device (MPR) corresponding to the bit line (BL). According to the usual features, the memory plate (PM) is located in a partial well (PW) at a floating potential, and the programming means (MPR) is configured to increase the potential of said partial well (PW) while simultaneously applying a programming pulse to the selected The bit line (BL) of the memory cell (CEL).

Description

technical field [0001] Various embodiments of the invention relate to memory, particularly electrically erasable and programmable (EEPROM) type non-volatile memory. Background technique [0002] In EEPROM memory, the logic value of a bit is stored in a memory cell, which typically includes an access transistor and a state transistor with a control gate and a floating gate. [0003] The programming or erasing of floating gate transistors consists in the transfer of charge through the tunneling effect ("Fowler-Nordheim effect") by means of a high voltage pulse Vp which may be of the order of 10 to 20 volts, typically of the order of 13 volts. Injected into or extracted from the gate of the transistor. [0004] This high voltage of 13 volts necessary to program EEPOM memory cannot be reduced and imposes tight constraints on technological process and product reliability. [0005] Indeed, lithography scaling (in other words increasing etch resolution) leads to lower operating v...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C16/10G11C16/22
CPCG11C16/10G11C16/225G11C16/0433G11C16/12G06F3/061G06F3/0625G06F3/0655G06F3/0688
Inventor F·塔耶特
Owner STMICROELECTRONICS (ROUSSET) SAS
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