Unlock instant, AI-driven research and patent intelligence for your innovation.

Chip packaging structure and packaging method

A packaging structure and packaging method technology, applied in the direction of electrical components, electric solid devices, circuits, etc., can solve the problems of chip surface damage, pollution, weak chip packaging structure, etc., and achieve the effect of increasing strength and avoiding damage and pollution

Pending Publication Date: 2017-08-25
CHINA WAFER LEVEL CSP
View PDF4 Cites 7 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] However, in the prior art, after peeling off the protective substrate from the wafer in advance, the surface of the chip may still be damaged and polluted in subsequent process steps such as dicing, and the strength of the package structure of the chip is also weak.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Chip packaging structure and packaging method
  • Chip packaging structure and packaging method
  • Chip packaging structure and packaging method

Examples

Experimental program
Comparison scheme
Effect test

other Embodiment approach

[0075] In other implementation manners, the chip 10 to be packaged can also be a photosensitive chip. In this case, in order to facilitate the sensing of light information by the pixels 100, the reinforcing layer 30 is set to be a transparent material. At this time, the chip 10 to be packaged may be an image sensor chip, and the pixel points 100 are used to sense light information incident through the transparent reinforcing layer 30 , and generate image information according to the light information. When the chip 10 to be packaged is a photosensitive chip, in order to ensure the imaging quality, the light transmittance of the strengthening layer 30 is set to be greater than 80%.

[0076] In order to ensure that the reinforcement layer has a good sealing effect, the thickness range of the reinforcement layer 30 is set to be 2 μm-40 μm inclusive, so as to effectively isolate water vapor and protect the pixel points 100 .

[0077] Generally, when the chip 10 to be packaged is p...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

PropertyMeasurementUnit
Thickness rangeaaaaaaaaaa
Hardnessaaaaaaaaaa
Login to View More

Abstract

The invention discloses a chip packaging structure and a packaging method. The packaging structure comprises a to-be-packaged chip, a strengthening layer, and a welding bump, wherein the to-be-packaged chip comprises a first surface and an opposite second surface, the first surface is provided with a sensing area and a first welding pad, and the first welding pad is electrically coupled with the sensing area; the strengthening layer covers the first surface of the to-be-packaged chip; the welding bump is arranged on the second surface of the to-be-packaged chip; the welding bump is electrically connected with the first welding pad and is electrically connected with an external circuit. As the strengthening layer is additionally arranged on the first surface of the to-be-packaged chip, in the case of cutting after removing a protection substrate, the surface of the to-be-packaged chip can be prevented from being damaged and polluted, and the strengthening layer can also enhance the strength of the to-be-packaged structure.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a chip packaging structure and a packaging method. Background technique [0002] With the continuous development of science and technology, more and more electronic devices are widely used in people's daily life and work, which brings great convenience to people's daily life and work, and has become an indispensable and important tool. [0003] The development trend of electronic equipment is miniaturization and portability. A major factor determining the miniaturization and portability of electronic equipment is the packaging design of chips in electronic equipment. The traditional chip packaging method usually uses wire bonding (Wire Bonding) for packaging, but with the rapid development of integrated circuits, longer leads make the product size unable to meet the ideal requirements. Therefore, wafer-level packaging (WLP: Wafer Level Package) has graduall...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): H01L23/00H01L23/498H01L21/48
CPCH01L23/49816H01L23/562H01L21/4853
Inventor 王之奇谢国梁胡汉青
Owner CHINA WAFER LEVEL CSP