Architecture and design method of fpga BRAM based on non-volatile memory

Abstract

The invention provides a nonvolatile memory-based FPGA BRAM architecture and a design method. The method comprises the steps of inputting a benchmark circuit and an architecture detail description; compiling the benchmark circuit into an RTL level circuit, performing logic synthesis on the RTL level circuit to generate a gate level circuit, and in a process of optimizing the gate level circuit, removing mapping of redundant connection wires in the RTL level circuit; performing packaging: packaging the optimized gate level circuit into logic blocks; performing optimal position arrangement on the generated logic blocks by utilizing an SA algorithm based on a tool VTR7.0; performing wiring: performing wiring on the generated logic blocks based on the tool VTR7.0, and after the logic blocks are subjected to the wiring, obtaining key path delays and bus lengths of the benchmark circuit; and performing performance assessment on the key path delays and the bus lengths, and outputting a minimum key path delay and a shortest bus length.

Description

technical field [0001] The invention relates to an FPGA BRAM architecture and a design method based on a nonvolatile memory. Background technique [0002] In the era of heterogeneous computing, from embedded devices to high-performance computing platforms, FPGA has become the choice favored by developers. The architecture also follows Moore's Law to provide more on-chip resources. However, the exponential increase in computing energy consumption (including video processing and machine learning algorithms, etc.) also brings more memory wall problems for FPGAs to implement memory-intensive functions. [0003] figure 1 It shows the traditional architecture of FPGA, where logic configuration modules CLB (configurable logic blocks), connection boxes CB (connecting boxes), switch boxes SB (switch boxes) and BRAM (blockRAMs) are distributed in the architecture, where BRAM is a configurable memory module , allowing fast data storage. In the past few generations of high-end Xilinx...

AI Technical Summary

Problems solved by technology

Although MLC technology greatly improves the storage density, because it takes two steps to read and write data in MLC STT-MRAM, the delay and power consumption of reading data from MLC or designing hard-bit is obviously higher than that of soft-bit

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