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Algorithm reconfiguration device and method

An algorithm and configuration parameter technology, applied in the field of communication, which can solve the problems of large algorithm granularity and poor system reconfiguration flexibility.

Inactive Publication Date: 2017-09-15
HARBIN ENG UNIV
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  • Application Information

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Problems solved by technology

[0004] The embodiment of the present invention provides an algorithm reconfiguration device and method to solve the problems of large algorithm granularity and poor system reconfigurable flexibility existing in the prior art

Method used

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  • Algorithm reconfiguration device and method
  • Algorithm reconfiguration device and method
  • Algorithm reconfiguration device and method

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Embodiment Construction

[0023] The following description and drawings illustrate specific embodiments of the invention sufficiently to enable those skilled in the art to practice them. The examples merely represent possible variations. Individual components and functions are optional unless explicitly required, and the order of operations may vary. Portions and features of some embodiments may be included in or substituted for those of other embodiments. The scope of embodiments of the present invention includes the full scope of the claims, and all available equivalents of the claims. Herein, various embodiments may be referred to individually or collectively by the term "invention", which is for convenience only and is not intended to automatically limit the scope of this application if in fact more than one invention is disclosed. A single invention or inventive concept. Herein, relational terms such as first and second etc. are used only to distinguish one entity or operation from another with...

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Abstract

The invention discloses an algorithm reconfiguration device. The device comprises an upper computer module, a software communication architecture (SCA) interlayer module, a base band processing module and a radio frequency module. The upper computer module is used for classifying algorithms into at least two sub-algorithms. The SCA interlayer module is used for operating an SCA. The SCA corresponds to the sub-algorithms and waveform application assemblies are set up. Each waveform application assembly is used for loading corresponding sub-algorithms. The upper computer module is used for configuring the waveform application assemblies to at least two of the upper computer module itself, the SCA interlayer module, the base band processing module and the radio frequency module. The invention further discloses an algorithm reconfiguration method.

Description

technical field [0001] The invention relates to the field of communication technology, in particular to an algorithm reconstruction device and method. Background technique [0002] At present, the main implementation method of the reconfigurable solution of the software-defined radio (English full name: Software Defined Radio, English abbreviation: SDR) general platform is the local dynamic reconfigurable technology, that is, through the field programmable gate with special cache logic resources The array (English full name: Field-Programmable Gate Array, English abbreviation: FPGA) performs reconfiguration of partial chip logic to realize reconstruction. The implementation plan mainly includes the design and synthesis of top-level modules, the design and synthesis of static modules, and the design and synthesis of each reconfiguration sub-module. The implementation process is relatively complicated, the development is difficult, and the cost is too high. [0003] The way o...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/445G06F9/44H04L29/08
CPCG06F8/60G06F8/70H04L67/2866H04L67/34
Inventor 窦峥刘彤林云张文旭张林波王杰
Owner HARBIN ENG UNIV
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