DRAM access method and bus

Abstract

Embodiments of the invention provide a DRAM (Dynamic Random Access Memory) access method and bus. The method comprises the steps of receiving an access instruction, wherein the access instruction comprises an access address, the access address comprises a physical address and added first and second fields, the first field is used for indicating an interleaving mode, the interleaving mode represents a selection mode of an access channel, the second field is used for indicating interleaving granularity, and the interleaving granularity represents the capacity of an address space under the access channel; according to the first field and the second field, determining the access channel and the address under the access channel; and according to the access channel and the address under the access channel, accessing a DRAM. According to the DRAM access method and bus provided by the embodiments of the invention, a control mode supporting multiple interleaving modes and interleaving granularities at the same time can be realized.

Description

technical field [0001] The present invention relates to the communication field, and more specifically, relates to a method and a bus for accessing a dynamic random access memory (DRAM). Background technique [0002] The bus storage architecture design of the application processor (Application Processor, AP) in the prior art, the central processing unit (Central Processing Unit, CPU) or the input / output (Input / Output, IO) peripherals access the fourth generation low-power dual When using Low PowerDouble Data Rate4 Dynamic Random Access Memory (LPDDR4 DRAM), it is usually necessary to connect 4 access channels for address interleaving access, and the interleaving granularity is also statically configured. [0003] Through the existing bus storage architecture, there are the following defects when the CPU or IO peripherals access the DRAM: when the AP is in some application scenarios that deal with low bandwidth requirements (for example, voice calls or audio playback, etc.), ...

AI Technical Summary

Problems solved by technology

[0003] Through the existing bus storage architecture, there are the following defects when the CPU or IO peripherals access the DRAM: when the AP is in some application scenarios that deal with low bandwidth requirements (for example, voice calls or audio playback, etc.), using the existing 4 The access channel interleaving mode accesses DRAM, and the power consumption of DRAM is higher than that of a single access channel; if a single access channel is reserved for a certain address space to access DRAM, the other three access channels parallel to this address segment cannot be used; If the CPU and IO devices (mainly media network protocols) have a large bandwidth flow in some scenarios, the 4-access channel interleaving mode of the prior art cannot isolate the access channels, resulting in bus congestion; and in some scenarios, due to different Internet Protocol (IP) accesses DRAM in different access modes, which will lead to unbalanced communication of DRAM

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