A chip packaging method and chip packaging structure
A chip packaging and chip technology, which is applied in the field of chip packaging methods and chip packaging structures, can solve problems such as output scale limitations
Inactive Publication Date: 2020-01-24
BOE TECH GRP CO LTD +1
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Problems solved by technology
[0004] However, due to the small size of substrates used in the semiconductor industry, generally 6 inches, 8 inches, and 12 inches, the output scale after packaging is limited
Method used
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Embodiment Construction
[0036] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of the present invention.
[0037] The embodiment of the present invention provides a chip packaging method, such as figure 1 Shown, including:
[0038] S10, such as figure 2 As shown, a peeling layer 20 is formed on the first panel-level substrate 10, and a rewiring layer 30 is formed on each preset area on the peeling layer 20, and the rewiring layers 30 located in different areas are insulated from each other; In the process of forming the rewiring layer 30, the ...
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Embodiments of the present invention provide a chip packaging method and a chip packaging structure, which relate to the field of semiconductor technology and can improve packaging efficiency and output efficiency. A chip packaging method, including: forming a peeling layer on a first panel-level substrate, and forming a rewiring layer in each preset area on the peeling layer, and the rewiring layers located in different areas are insulated from each other. ; In the process of forming the rewiring layer, a first dielectric layer is also formed; the chip and the pillar connected to the chip are connected through the solder cap on the pillar and the rewiring layer formed in the preset area. Connect the wiring layer; encapsulate the chip to form an encapsulation layer; remove the first panel-level substrate and the peeling layer, and form solder balls on one side of the rewiring layer.
Description
Technical field [0001] The present invention relates to the field of semiconductor technology, in particular to a chip packaging method and a chip packaging structure. Background technique [0002] With the continuous development of integrated circuit technology, electronic products are becoming more and more miniaturized, intelligent and highly reliable, and integrated circuit packaging directly affects the performance of integrated circuits, electronic modules and even the whole machine, and the integrated circuit chips are gradually reduced , With the continuous improvement of integration, higher and higher requirements are put forward for integrated circuit packaging. [0003] The traditional chip packaging in the semiconductor industry mainly includes the following processes: cutting the chips on the wafer, dividing them into individual chips, re-arranging the qualified chips on the substrate according to the rules, and then packaging to form a rewiring layer ( Re-Distributio...
Claims
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IPC IPC(8): H01L23/488H01L21/60H01L21/78
CPCH01L24/11H01L24/13H01L24/97H01L2224/0231H01L2224/02331H01L2224/02335H01L2224/02381H01L2224/11001H01L2224/13016H01L2224/13024H01L2224/97H01L23/3128H01L21/561H01L21/568H01L23/49816H01L23/3135H01L2224/05647H01L2224/0391H01L2224/051H01L2224/0401H01L24/05H01L24/03H01L24/94H01L2224/94H01L2224/11849H01L2224/03002H01L2224/11002H01L2224/81005H01L2224/95H01L24/95H01L2224/95001H01L2924/181H01L24/81H01L24/16H01L2224/16227H01L2224/131H01L2924/00014H01L2224/03H01L2224/11H01L2224/81H01L2924/014H01L21/566H01L21/4825H01L21/78H01L2224/11462H01L2224/13147H01L21/563
Inventor 曲连杰
Owner BOE TECH GRP CO LTD