3bit streamline-type ADC's sequential control method

Abstract

The invention proposes a 3bit streamline-type ADC's sequential control method, belonging to the technical field of analog integrated circuits. According to the invention, through the utilization of four clock control signals, the working state of a 3bit streamline-type ADC is divided into a sampling stage and an amplifying stage. In the sampling stage, an MDAC samples the input signals; a sub-ADC samples the input signals and stores the difference between the input signals and the reference voltage of the sampled sub-ADC in the amplifying stage of a previous working cycle, wherein after the difference is processed by a comparator, a 7-bit thermometer code is obtained and a 3-bit digital code is obtained after the encoding as the digital output signals for the 3bit streamline-type ADC. In the amplifying stage, the sub-ADC the reference voltage of the sub-ADC for use in the sampling stage of a next working cycle. The MDAC samples the reference voltage of the MDAC and stores the difference between the MDAC reference voltage and the sampled input signals, wherein after the difference is calculated and amplified, a 3bit streamline-type ADC simulated output signal can be obtained. According to the invention, adjustment can be made to the sequence, which effectively increases the time for the establishing of an operation amplifying device.

Description

technical field [0001] The invention belongs to the technical field of analog integrated circuits, and in particular relates to a timing control method of a 3-bit pipeline ADC. Background technique [0002] In recent years, with the rapid development of digital signal processing technology, digital signal processing technology is widely used in various fields, so the performance of the analog-to-digital converter (Analog-to-Digital Converter, ADC) as a bridge between analog and digital systems Higher and higher requirements have also been raised. The system not only needs to improve the sampling rate and quantization precision of the analog-to-digital converter, but also hopes to improve the conversion efficiency of the analog-to-digital converter and reduce its power consumption. [0003] Pipeline ADC is currently the most obvious trade-off advantage in speed, accuracy, power consumption and area among ADCs. The basic idea of ​​the pipeline analog-to-digital converter is ...

AI Technical Summary

Problems solved by technology

However, under the premise that the same process conditions remain unchanged, the bandwidth of the operational amplifier cannot be effectively improved by increasing power consumption.

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