3bit streamline-type ADC's sequential control method

A pipelined, timing-controlled technology, applied in signal transmission systems, instruments, electrical components, etc., can solve problems such as ineffectively increasing operational amplifier bandwidth and increasing power consumption, reducing power consumption and area, and reducing the number of stages used , The effect of improving ADC performance

Active Publication Date: 2017-10-24
UNIV OF ELECTRONIC SCI & TECH OF CHINA
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  • Claims
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Problems solved by technology

However, under the premise that the same process conditions remain unchanged, the bandwidth

Method used

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  • 3bit streamline-type ADC's sequential control method
  • 3bit streamline-type ADC's sequential control method
  • 3bit streamline-type ADC's sequential control method

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[0027] The present invention will be described in detail below in conjunction with the drawings and specific embodiments.

[0028] The 3bit pipeline ADC used in this embodiment includes sub-ADC and MDAC, figure 2 Shown here is a schematic diagram of the structure of the MDAC in this embodiment, including an operational amplifier, two feedback capacitors Cf and sixteen sampling capacitors. The two input terminals of the operational amplifier are each connected to eight sampling capacitors Cs1-Cs8, wherein the sampling capacitor Cs1 One plate is connected to an input terminal of the operational amplifier, and the other plate is connected to the input signal Vin or the common mode voltage signal Vcm through a switch; one plate of the sampling capacitor Cs2-Cs8 is connected to an input terminal of the operational amplifier, and the other plate passes through The switch is connected to the input signal Vin or the reference voltage ±VREF of the MDAC. Two feedback capacitors Cf are res...

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Abstract

The invention proposes a 3bit streamline-type ADC's sequential control method, belonging to the technical field of analog integrated circuits. According to the invention, through the utilization of four clock control signals, the working state of a 3bit streamline-type ADC is divided into a sampling stage and an amplifying stage. In the sampling stage, an MDAC samples the input signals; a sub-ADC samples the input signals and stores the difference between the input signals and the reference voltage of the sampled sub-ADC in the amplifying stage of a previous working cycle, wherein after the difference is processed by a comparator, a 7-bit thermometer code is obtained and a 3-bit digital code is obtained after the encoding as the digital output signals for the 3bit streamline-type ADC. In the amplifying stage, the sub-ADC the reference voltage of the sub-ADC for use in the sampling stage of a next working cycle. The MDAC samples the reference voltage of the MDAC and stores the difference between the MDAC reference voltage and the sampled input signals, wherein after the difference is calculated and amplified, a 3bit streamline-type ADC simulated output signal can be obtained. According to the invention, adjustment can be made to the sequence, which effectively increases the time for the establishing of an operation amplifying device.

Description

technical field [0001] The invention belongs to the technical field of analog integrated circuits, and in particular relates to a timing control method of a 3-bit pipeline ADC. Background technique [0002] In recent years, with the rapid development of digital signal processing technology, digital signal processing technology is widely used in various fields, so the performance of the analog-to-digital converter (Analog-to-Digital Converter, ADC) as a bridge between analog and digital systems Higher and higher requirements have also been raised. The system not only needs to improve the sampling rate and quantization precision of the analog-to-digital converter, but also hopes to improve the conversion efficiency of the analog-to-digital converter and reduce its power consumption. [0003] Pipeline ADC is currently the most obvious trade-off advantage in speed, accuracy, power consumption and area among ADCs. The basic idea of ​​the pipeline analog-to-digital converter is ...

Claims

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Application Information

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IPC IPC(8): H03M1/46
CPCH03M1/462
Inventor 唐鹤毛祚伟高昂彭传伟彭析竹
Owner UNIV OF ELECTRONIC SCI & TECH OF CHINA
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