Timing control method of 3bit pipelined adc

Abstract

A timing control method for a 3-bit pipelined ADC belongs to the technical field of analog integrated circuits. The present invention uses four clock control signals to divide the working state of the 3bit pipelined ADC into a sampling stage and an amplification stage. During the sampling stage, the MDAC samples the input signal, and the sub-ADC samples the input signal and stores the input signal and the previous working cycle amplification stage. The difference of the reference voltage of the sub-ADC sampled in the middle, the difference is processed by the comparator to obtain a 7-bit thermometer code and after encoding, a 3-digit digital code is obtained as the digital output signal of the 3-bit pipeline ADC; during the amplification stage, the sub-ADC The reference voltage of the sub-ADC is sampled for use in the sampling phase of the next working cycle; the MDAC samples the reference voltage of the MDAC and stores the difference between the reference voltage of the MDAC and the input signal sampled during the sampling phase of the working cycle, and the difference is calculated After amplification, the analog output signal of the 3bit pipeline ADC is obtained. The invention adjusts the time sequence, effectively increasing the establishment time of the operational amplifier.

Description

technical field [0001] The invention belongs to the technical field of analog integrated circuits, and in particular relates to a timing control method of a 3-bit pipeline ADC. Background technique [0002] In recent years, with the rapid development of digital signal processing technology, digital signal processing technology is widely used in various fields, so the performance of the analog-to-digital converter (Analog-to-Digital Converter, ADC) as a bridge between analog and digital systems Higher and higher requirements have also been raised. The system not only needs to improve the sampling rate and quantization precision of the analog-to-digital converter, but also hopes to improve the conversion efficiency of the analog-to-digital converter and reduce its power consumption. [0003] Pipeline ADC is currently the most obvious trade-off advantage in speed, accuracy, power consumption and area among ADCs. The basic idea of ​​the pipeline analog-to-digital converter is ...

AI Technical Summary

Problems solved by technology

However, under the premise that the same process conditions remain unchanged, the bandwidth of the operational amplifier cannot be effectively improved by increasing power consumption.

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