System-in-package method and package unit thereof
A technology of system-level packaging and resistor elements, which is applied in the manufacture of electrical components, electrical solid-state devices, semiconductor/solid-state devices, etc., can solve the problems of high manufacturing cost and complex design of system-level packaging, and achieve good IC design flexibility and reliability performance, improve anti-interference design, and simplify layout
Inactive Publication Date: 2017-11-21
BEIJING CHINA ECNET +1
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Problems solved by technology
[0006] In view of the deficiencies of the above-mentioned prior art, the purpose of the present invention is to provide a system-in-package method and its packaging unit, aiming to solve the problems of complex design and high manufacturing cost of system-in-package in the prior art
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[0030] The invention provides a system-level packaging method and a packaging unit thereof. In order to make the object, technical solution and effect of the present invention more clear and definite, the present invention will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.
[0031] Such as figure 1 Shown is an example of the assembly flow of a system-in-package (SIP) unit. That is to assemble a variety of IC products (modules or chips with specific functions), discrete components (capacitors, resistors, active components, etc.), multi-chip packages (MCP) and multi-chip modules (MCM) into a printed circuit board .
[0032] First, the Know Good Die KGD is assembled into different packages, such as Small Outline J-Lead (SOJ), Quad Flat Pack (QFP), Pin Grid Array (PGA), Ball Grid...
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The invention discloses a system-in-package method and a package unit thereof. The method includes the steps of arranging capacitor elements and resistor elements independently to form a capacitor-resistor array; forming a plurality of optimized chips by a predetermined package form; stacking the capacitor-resistor array and the optimized chips to form a first 3D stacked bare die; taking an array comprising active devices and integrated circuits processed by different manufacturing technologies as a second bare die, and stacking with the remaining optimized chips to form a second 3D stacked bare die; and assembling the first and second 3D stacked bare dies with a multi-chip package unit and a multi-chip module into a system-in-package unit. The package method of independent arrangement provides higher IC design flexibility and reliability. And the second bar die with the active components and the various ICs is further developed as, together with other optimized chips, a layer to be stacked into the system-in-package unit, without the use of a printed circuit board, and the cost and size can be further reduced.
Description
technical field [0001] The invention relates to the technical field of chip packaging, in particular to a system-in-package method and a packaging unit thereof. Background technique [0002] In the traditional chip packaging process, IC products can be assembled in various packaging structures through a variety of different packaging methods. It is then packed into boxes or modules to form the final factory product. With the continuous development of technology, the market has higher and higher requirements for the integration and volume of IC products. Therefore, based on the emergence of new multi-chip packaging and modular technologies (MCP, MCM, etc.), more components can be set and integrated in a single module. [0003] The system-in-package (SIP) is the latest technology recently, which can install a variety of different components on a common base, integrate multiple functional modules on a single chip, and connect them to each other to perform system-level functio...
Claims
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IPC IPC(8): H01L25/16H01L21/98
CPCH01L25/16H01L25/50
Inventor 萧建成
Owner BEIJING CHINA ECNET