System-on-a-programmable-chip (SoPC)

Abstract

The invention discloses a system-on-a-programmable-chip (SoPC), and relates to integrated-circuit technology. The system-on-a-programmable-chip includes an FPGA and an SOC part. A slave port, a master port, an int port and a config port of the FPGA are directly connected with a high-speed parallel system bus matrix in the SOC part. IO ports of the FPGA are connected with an IO reuse module. The system fully exerts respective technical advantages of a CPU subsystem and the FPGA. Built-in FPGA equivalent-logic is large in a scale, and high in work frequency. A CPU core is mainly responsible for orderly executing logic operations and transaction management. The FPGA is responsible for large-scale complex parallel operating. All of CPU and FPGA tasks can be realized through programming, and the scope of application of a chip is greatly expanded.

Description

technical field [0001] The present invention relates to integrated circuit technology. Background technique [0002] SoPC (System-on-a-Programmable-Chip, programmable system on a chip) has two main technical routes at home and abroad: one is FPGA embedded in CPU hard core, and the other is FPGA embedded in CPU soft core. [0003] The technical way of embedding FPGA into CPU hard core is represented by XILINX. Initially, XILINX was represented by V5FX series, which embedded PowerPC hard core in FPGA. With the advancement of technology, XILINX has developed the SoPC chip of the Zynq-7000All ProgrammableSoC series, which adopts the new architecture of SoC+FPGA. In the SoPC of this architecture, the SoC and the FPGA are completely independent, and are internally interconnected through various efficient buses. It uses a high-performance embedded processor, and integrates special-purpose hardware and general-purpose peripherals without occupying FPGA logic resources. With this...

AI Technical Summary

Problems solved by technology

However, in the prior art, the disadvantage of embedding the FPGA into the CPU hard core is that the interconnection structure between the FPGA and the CPU is single, there are few data paths, the bandwidth of the data bus is small, and the efficiency and flexibility are not enough.

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