Processor chip emulator with nonvolatile memory

Abstract

The invention discloses a processor chip emulator with a nonvolatile memory. Code coverage configuration is written to a control logic module by a monitoring module through a write channel; accordingto the code coverage configuration, if a received write operation target address is in the code coverage configuration, the control logic module performs a transparent channel function and directly connects a first standard data/address bus connected with a processor core with a second standard data/address bus connected with an SRAM equivalently in terms of function and performance; if the received write operation target address is not in the code coverage configuration, the control logic module can emulate a write operation sequential control function and write operation sequential control performance of an equivalent nonvolatile memory and can be used in cooperation with the SRAM to be equivalent to a write operation time sequence and function and write operation performance of the nonvolatile memory in a product chip. According to the processor chip emulator, not only is the consistency of the function and the performance of the emulator guaranteed, but achievement and usage modesof a system are simplified.

Description

technical field [0001] The invention relates to a processor chip emulator, in particular to a processor chip emulator with non-volatile memory. Background technique [0002] There is a user program developed by the user in the processor chip. In the writing and debugging of the user program, the tool used is generally an emulator. The emulator uses an emulation chip containing various functions of the product processor chip to simulate the working behavior of the product processor chip, and the emulation chip and other parts of the emulator (program memory for storing user programs, data memory for storing data, and user The integrated development environment on the computer, etc.) cooperates with the integrated development environment on the computer to realize the writing, compiling, downloading, simulation operation and various debugging functions of the user program. [0003] Many processor chips have non-volatile memories, such as EEPROM (Electrically Erasable Programm...

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Problems solved by technology

Therefore, there are usually two implementation methods for existing emulators. The first one directly makes the non-volatile memory into pure SRAM characteristics in the emulator to ensure that it can be directly operated through the standard integrated development environment, but it will cause emulator The internal non-volatile memory is inconsistent with the product chip in terms of function and performance; the second method is to replace the non-volatile memory with SRAM plus equivalent control logic to ensure the consistency of functional performance, but it is necessary to ask the integrated development environment manufacturer Add patches for the size and characteristics of the target chip's non-volatile memory, or develop and provide the non-volatile memory code on the integrated development environment to download the boot project (for example, the FLM and FLX project formats supported by KEIL), for your own code The memory code area size and memory writing characteristics of the project compilation result can be customized. After compilation, special machine code files (for example, files with the suffixes of KEIL and FLX) are generated. Before downloading the code, download the code to guide the download of the project machine code file. Go to the chip's XRAM (on-chip expanded RAM, external random access memory) area and execute it. According to the operation timing requirements of the on-chip non-volatile memory, write the code boot into the designated area of ​​the chip's non-volatile memory. The process It is complex and needs to be written according to the timing requirements, and the efficiency is low. It is also necessary to continuously modify and adjust the settings of the code download boot project and recompile to generate machine code files according to the size change of the code area in the code project compilation result. Consistency in function and performance of volatile memory, but cumbersome to use and low in efficiency

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