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High-speed signal wire optimization method and system under condition of compact structure and space

A high-speed signal and optimization method technology, applied in special data processing applications, instruments, electrical digital data processing, etc., can solve the problem that high-speed signal lines cannot meet the shortest line length, etc., to improve signal integrity, reliable design principles, The effect of broad application prospects

Inactive Publication Date: 2018-01-19
ZHENGZHOU YUNHAI INFORMATION TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The purpose of the present invention is to provide a high-speed signal line optimization method and system for tight structural space to solve the above technical problems

Method used

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  • High-speed signal wire optimization method and system under condition of compact structure and space
  • High-speed signal wire optimization method and system under condition of compact structure and space
  • High-speed signal wire optimization method and system under condition of compact structure and space

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Embodiment 1

[0040] Example 1 takes PCIE 3.0 signals as an example to compare the design requirements, from image 3 The case 1 link shown is a link with a path length of 4 inches and a via stub 60 mil. Case 2 is a link with a link length of 3 inches and a via stub 60 mil. It is found that the link length of the case 2 is 3 inches. If the minimum trace length of 4 inches is not met, further judge whether the via stub column in Case 2 exceeds the set via stub standard value;

[0041] If the via stub standard value is 40 mil, the 60 mil via stub of case 2 exceeds the set via stub standard value. After the via stub column of case 2 is back drilled, case 3, link length is obtained It is still 3inch, but the via short post becomes 10mil after back drilling;

[0042] If the standard value of the via stub is 65 mil, then the 60 mil via stub of Case 2 does not exceed the set standard value of the via stub, and use a plate with a dielectric constant lower than the standard material epoxy resin-glass FR-...

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Abstract

The invention provides a high-speed signal wire optimization method and system under the condition of compact structure and space. The method comprises the following steps that 1, by contrasting a PCBdesign requirement, high-speed signal links, which do not meet a shortest wiring requirement, in high-speed link signal wires are found out; 2, whether or not via hole short columns exist in the high-speed signal links and whether or not the via hole short columns exceed a set standard value are judged; if yes, the via hole short columns are subjected to backdrill; 3, if no via hole short columnexists, or the via hole short columns exist but do not exceed the set standard value, a PCB board of which the dielectric constant is lower than that of a standard material is selected; 4, through simulation comparison, the properties of the high-speed signal links, which do not meet the shortest wiring requirement, before treatment and after treatment are verified. According to the high-speed signal wire optimization method and system under the condition of the compact structure and space, a backdrill method or a method of lowering the dielectric constant of board cards and board materials isadopted, so that reflection in the links is reduced, the completeness of signals is improved, and the space problem of bypassing of compact board cards is solved.

Description

Technical field [0001] The invention belongs to the field of high-speed signal line wiring of a server mainboard, and particularly relates to a method and system for optimizing high-speed signal lines with tight structural space. Background technique [0002] In server motherboard design, high-speed lines usually limit the shortest length, because in transmission line theory, the rise time is less than one-sixth of the transmission line delay, which considers the edge of reflection, that is, the line length is too short, and the rise time is less than one-sixth of the transmission line. Delay, there will be serious reflections, resulting in reduced signal integrity. Designers usually limit the signal trace length according to the signal rate during solution evaluation, but usually take into account the influence of via stubs and other factors in the signal link, which aggravate signal reflection, so the shortest trace length is usually limited to 4 inches . When designing serve...

Claims

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Application Information

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IPC IPC(8): G06F17/50
Inventor 李永翠
Owner ZHENGZHOU YUNHAI INFORMATION TECH CO LTD