A method for manufacturing a three-dimensional memory device and its device structure

Abstract

The invention provides a manufacturing method of a three-dimensional memory device and a device structure thereof. By optimizing the graphic design of a staircase divide scheme, the influence of lithography and etching processes on the graphical deformation and distortion of the staircase divide scheme is reduced, the effective contact area of the stair region is substantially increased, and the contact failure of the electrical connecting lines of 3D NAND is reduced.

Description

technical field [0001] The invention relates to the field of semiconductor devices and their manufacture, in particular to a manufacturing method of a three-dimensional flash storage device and its device structure. Background technique [0002] With the continuous improvement of market demand for memory capacity, the number of memory cells that can be provided per unit area by traditional memory based on planar or two-dimensional structures is approaching the limit, which cannot further meet the market demand for larger capacity memory. Just like several bungalows built on a limited plane, these bungalows are neatly arranged, but as the demand continues to increase, the number of bungalows continues to blow out, but in the end this limited plane can only accommodate a certain number of bungalows. Cannot continue to increase. In particular, planar flash memory (NAND) is approaching its practical expansion limit, which brings severe challenges to the semiconductor memory ind...

AI Technical Summary

Problems solved by technology

[0006] However, in the subsequent step etching process, the independent partition steps will be deformed to a certain extent, such as Figure 4-5 As shown, the end of the independent partition pattern step (SSDS) away from the core region (Core) of the storage device is enlarged and deformed due to the cumulative etching process, which makes the original rectangular step pattern design become after the cumulative etching process Oblique trapezoidal figure, which affects the implementation of the later electrical connection contact hole process

like Image 6 As shown, since the step is formed after the cumulative etching process, the step width on the side close to the core area is narrow, and the step width on the side away from the core area is wide, so that a part of the contact hole pattern on the edge is in the The narrow step area part cannot realize the opening operation of lithography and etching, even the wider step area away from the core area, because the step width is still uneven, resulting in a part of the contact hole pattern cannot be completely completed. Realize lithography and etching opening operations

This situation causes the gates of the memory cells of some three-dimensional memory devices to fail to effectively form a contact hole electrically connected to it, and forms an invalid contact hole (Fail Contact), thereby affecting the normal operation of the device.

[0007] In addition, if Figure 7 As shown, in the process of forming the pattern of the core area (Core) and SSDS, due to the closeness of the photoresist to each other, there will be certain interference problems, and the pattern will be distorted in the photolithography process: in the subsequent etching process , this distortion will be brought to the back step, and finally the contact hole cannot fall on the step correctly, forming an invalid contact hole (Fail Contact), resulting in the failure of the electrical connection

[0008] In summary, when the structure of the three-dimensional memory device becomes more and more complex, the number of step layers increases, and the steps change from one-way distribution to two-way distribution, the previous etching process of the core area and the step area cannot meet its pattern. Due to the various deformations of the step pattern in the etching process, the subsequent process of forming contact holes cannot be correctly implemented on each step region

There is currently no effective solution to this problem, which seriously restricts the further development of 3D memory devices.

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