30results about How to "Reduce contact failure" patented technology

The semiconductor device includes a transistor and a capacitor element which is electrically connected to a gate of the transistor. Charge held in the capacitor element according to total voltage of voltage corresponding to the threshold voltage of the transistor and image signal voltage is once discharged through the transistor, so that variation in current flowing in the transistor or mobility of the transistor can be reduced.

A pair of contact members 10, 10 coming into contact with both of a front-surface and an undersurface of a substrate 2 by elastic forces, comprise a pair of first contact points 11, 11 getting, when the substrate 2 is inserted, apart from each other due to a thickness of the substrate 2, resisting the elastic forces, and a pair of second contact points 12, 12 coming into, when the pair of first contact points 11, 11 are biased by the elastic forces in such a direction to get close to each other within a hole 21 opened at both of the front-surface and the undersurface of the substrate 2, contact with both of the front-surface and the undersurface of the substrate 2 in a way that interlocks with the first contact points 11,11.

The invention provides a manufacturing method of a three-dimensional memory device and a device structure thereof. By optimizing the graphic design of a staircase divide scheme, the influence of lithography and etching processes on the graphical deformation and distortion of the staircase divide scheme is reduced, the effective contact area of the stair region is substantially increased, and the contact failure of the electrical connecting lines of 3D NAND is reduced.

A lens mounting apparatus includes a base including an opening, wherein a lens including a connection part is inserted and attached, an annular frame including a notch provided on a part of an outer periphery, a socket electrically connected to the connection part of the lens, and a first elastic member provided to urge the socket from the outer periphery toward a center of the annular frame. The annular frame is configured to fix the lens inserted and attached into the base by rotating the annular frame in one direction by a predetermined angle. When the annular frame does not fix the lens, the notch does not face the socket. When the annular frame fixes the lens, the notch faces the socket, and the socket is electrically connected to the connection part of the lens by an urging force of the first elastic member.

The invention relates to the technical field of high-voltage power distribution cabinets, and discloses a high-voltage power distribution cabinet for new energy vehicles, which includes a power distribution cabinet. The power distribution cabinet includes a cabinet body. The inner wall is fixedly connected with a dust-proof net, the front side of the cabinet body is connected with a cabinet body door through hinge rotation, the right end of the front side side of the cabinet body door is fixedly connected with a handle, and the front and rear ends of the right side of the cabinet body are provided with T-shaped chutes. The inner wall of the T-shaped chute of the cabinet is slidably connected with a T-shaped clamping rod, the right side of the T-shaped clamping rod is fixedly connected with the right cover plate, and the inner rear end of the cabinet is provided with a wire fixing device, which solves the problem of existing The electric cabinet does not have a special device for combing the wires, which makes the wires inside the distribution cabinet scattered and piled up easily to accumulate heat, and the surface of the wires will accumulate thick dust after long-term use, which is not easy to distinguish, making maintenance personnel When the electric cabinet is repaired, it is troublesome to find the wires.

In a semiconductor device and a method of manufacturing the same, a conductive structure is formed on an active region defined by a device isolation layer on a semiconductor substrate. The conductive structure includes a gate pattern and source / drain regions adjacent to the gate pattern. A first semiconductor layer is formed on the active region by a selective epitaxial growth (SEG) process. An amorphous layer is formed on the first semiconductor layer. A second semiconductor layer is formed from a portion of the amorphous layer by a solid-phase epitaxy (SPE) process. Elevated structures are formed on the source / drain regions by removing a remaining portion of the amorphous layer from the substrate, so the elevated structure includes the first semiconductor layer and the second semiconductor layer stacked on the first semiconductor layer. The device isolation layer may be prevented from being covered with the elevated structures, to thereby prevent contact failures.