RAM
A random access memory and converter technology, applied in the field of memory, can solve problems such as unreliable high-speed signals, easy distortion of signals, and distortion received by random access memory, and achieve the effect of solving transmission high-speed signal distortion, improving performance, and eliminating intersymbol interference
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Embodiment 1
[0089] Such as figure 1 As shown, this embodiment provides a random access memory, including a serial-to-parallel converter 120, and also includes:
[0090] The continuous-time linear equalizer 110 has a first input end that is a random access memory signal receiving end, and also has a first output end that is communicatively connected to the serial-to-parallel converter, and is used to perform channel compensation gain on the input signal and channel-compensated sending a signal to the serial-to-parallel converter;
[0091] The decision feedback equalizer 130 has a second input terminal communicatively connected to the continuous-time linear equalizer 110 and a second output terminal communicatively connected to the serial-to-parallel converter 120 for eliminating intersymbol interference of the input signal.
[0092] In this embodiment, a continuous-time linear equalizer 110 and a decision feedback equalizer 130 are provided on the random access memory. The continuous-tim...
Embodiment 2
[0126] Such as Figure 5 As shown, based on embodiment 1, the random access memory described in this embodiment also includes:
[0127] A data slicer 140, the input end of the data slicer 140 is connected to the output end of the continuous time linear equalizer 110, the output end of the data slicer 140 is connected to the input end of the decision feedback equalizer 130, for for quantizing the input signal;
[0128] A clock data recovery circuit 150, the input end of the clock data recovery circuit 150 is connected to the output end of the serial-to-parallel converter 120 for extracting phase information from the high-speed serial signal;
[0129] A phase-locked loop 160, the input of the phase-locked loop 160 is connected to the output of the clock data recovery circuit 150, the output of the phase-locked loop 160 is connected to the data slicer 140 and the decision feedback The equalizer 130 is connected to automatically control the phase synchronization of different ele...
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