Register alias table recovery method

Abstract

The invention discloses a register alias table recovery method, comprising: upon cancelling of a command, updating reorder buffer stations; from an item pointed by a head pointer of a queue of the reorder buffer stations, dividing the queue into multiple groups; transmitting, in each cycle, information of one group for register alias table recovery to a mapping relation recovery module corresponding to a logic register; searching the transmitted group of information in reverse order, and judging whether the information for register alias table recovery is satisfactory; if yes, generating update signals for corresponding items of a register alias table, and transmitting physical addresses of target registers of the corresponding items in rename buffer stations to the register alias table; subjecting the mapping relation recovery modules used by the different groups of the rename buffer stations to time division multiple access. The register alias table recovery method has the advantagethat area is decreased and time series performance is improved in case that reorder buffers have great depth.

Description

technical field [0001] The invention relates to the technical field of register processing, in particular to a method for restoring a register alias table. Background technique [0002] Modern superscalar processors make extensive use of branch prediction, register renaming, and speculative execution techniques to improve operating efficiency. Among them, the branch prediction technology enables the processor to predict the branch target and fetch instructions in advance according to the historical information of the program operation before the branch instruction is executed; the register renaming technology can eliminate the problem caused by the insufficient number of logical registers through redundant physical registers. Data read-before-write correlation and write-write correlation allow more instructions to be executed in parallel; speculative execution can execute instructions prefetched according to branch prediction in advance. The joint use of these three technol...

AI Technical Summary

Problems solved by technology

But this invention still has some limitations, the most prominent is that the search process to the reordering buffer is carried out sequentially, if the depth of reordering is larger, then the search logic will also take a larger time, and the longer logic chain The timing overhead may not be completely covered by the idle time of the new instruction fetch instruction to reach the pipeline register renaming stage

Images