Creating method and system for standard cell library

Abstract

The embodiment of the invention provides a creating method and system for a standard cell library. By determining the classification of a basic logical unit, at least one classification unit is generated, and then the amount of driving strength of each classification unit is determined, and finally the component size of the basic logical unit is determined. Each basic logical unit of the standardcell library is reasonably allocated by the creating method and system, effectively achieving the balance of timing sequence and area of a chip during an ASIC design process can be guaranteed, and chip area waste caused by adopting multiple units combinations which is due to the lack of corresponding drive can be prevented. In addition, a matching ratio of the basic logical unit is defined, a schematic diagram of a unit circuit is convenient to quickly achieve, the time of design and development of the standard cell library is effectively shorten, a good drive consistency is provided, the rapid convergence of critical path timing sequence of the chip is facilitated, the number of invalid iterations of repairing timing sequence violations in the processes of logic synthesis and locating andwiring is obviously reduced, and the efficiency of designing a large scale integrated circuit is improved.

Description

technical field [0001] The invention relates to the technical field of integrated circuit design, and more specifically, to a method and system for creating a standard cell library. Background technique [0002] The standard cell library is a collection of combinational logic cells, sequential logic cells, and special cells; it contains data such as cell netlists, cell symbols, cell layouts, logic function models, and comprehensive library models. It is the basic database for large-scale integrated circuit design. ASIC design based on standard cells can greatly improve design efficiency, speed up the time for products to enter the market, and has the advantages of low cost and short cycle. The performance of the standard cell library determines the characteristics of the chip area, timing and power consumption. With the improvement of integration and working speed of monolithic integrated circuits, designing and developing a high-integration and high-speed standard cell lib...

AI Technical Summary

Problems solved by technology

[0006] The inventor found that, using the existing method, the logic function and timing characteristics of the standard cell can be determined through simulation, but the quantity allocation and device size ratio of the overall driving capability of the standard cell library cannot be obtained through circuit simulation

That is, the consistency of the driving ability in the development process of the existing standard cell library is poor

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