Memory cells, methods of forming an array of two transistor-one capacitor memory cells, and methods used in fabricating integrated circuitry

Abstract

The present invention relates to memory cells, methods of forming an array of two transistor-one capacitor memory cells, and methods used in fabricating integrated circuitry. A memory cell comprises first and second transistors laterally displaced relative one another. A capacitor is above the first and second transistors. The capacitor comprises a container-shape conductive first capacitor node electrically coupled with a first current node of the first transistor, a conductive second capacitor node electrically coupled with a first current node of the second transistor, and a capacitor dielectric material between the first capacitor node and the second capacitor node. The capacitor dielectric material extends across a top of the container-shape first capacitor node. Additional embodiments and aspects, including method, are disclosed.

Description

technical field [0001] Embodiments disclosed herein relate to memory cells, methods of forming memory cells, and methods for fabricating integrated circuits. Background technique [0002] Dynamic Random Access Memory (DRAM) is used in modern computing architectures. DRAM offers structural simplicity, low cost, and speed advantages over other types of memory. [0003] Currently, DRAMs typically have individual memory cells (so-called 1T-1C memory cells) that combine a capacitor with one of the transistor's source / drain regions, where the capacitor is coupled with one of the transistor's source / drain regions. One of the limiting factors in the scalability of current 1T-1C configurations is the difficulty of incorporating capacitors with sufficiently high capacitance into highly integrated architectures. Accordingly, it is desirable to develop new memory cell configurations suitable for incorporation into highly integrated modern memory architectures. [0004] While the pres...

AI Technical Summary

Problems solved by technology

One of the limiting factors in the scalability of current 1T-1C configurations is the difficulty of incorporating capacitors with sufficiently high capacitance into highly integrated architectures

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