A dynamic reconfiguration controller for fpga against single event effect

An anti-single event effect and dynamic reconfiguration technology, which is applied to architectures, instruments, and computers with a single central processing unit, can solve problems that affect the correct operation of the system, errors in the reconstruction process, and high sensitivity to single event effects, etc. question

Active Publication Date: 2021-05-14
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Traditional dynamic reconfiguration controllers are mainly implemented based on complex microprocessors (such as MicroBlaze, PowerPC, and ARM). Microprocessor-based dynamic reconfiguration controllers are highly complex, occupy a lot of resources, and require a large number of Features such as SRAM memory implementation make it highly sensitive to single event effects
Failure of the reconfiguration controller will cause errors in the entire reconfiguration process, affecting the correct operation of the system

Method used

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  • A dynamic reconfiguration controller for fpga against single event effect
  • A dynamic reconfiguration controller for fpga against single event effect
  • A dynamic reconfiguration controller for fpga against single event effect

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Embodiment

[0024] For the convenience of description, the relevant technical terms appearing in the specific implementation are explained first:

[0025] SRAM (Static Random Access Memory): static random access memory;

[0026] FSM (Finite State Machine): finite state machine;

[0027] ICAP (Internal Configuration Access Port): internal configuration access channel;

[0028] MV (Majority Voter): majority voter

[0029] BRAM (Block Random Access Memory): block memory;

[0030] figure 1 It is a schematic diagram of an FPGA dynamic reconfiguration controller for anti-single event effect of the present invention.

[0031] In this example, if figure 1 As shown, the present invention is an anti-single event effect FPGA dynamic reconfiguration controller, including: FSM command state machine, core control module, memory controller, ICAP unit and off-chip memory.

[0032] Below we combine figure 1 In detail, specifically:

[0033] FSM command state machine, including all reconstruction m...

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Abstract

The invention discloses an FPGA dynamic reconfiguration controller capable of resisting single event effects, which is composed of an FSM command state machine, a core control module, a storage controller and an internal access interface ICAP, and then cooperates with each component module, Thereby avoided the use of complicated microprocessor, saved a large amount of FPGA resources, reduced the sensitivity to single event effect; In this way, the self-healing design of the reconfigurable controller is realized, so that the controller has the ability of fault self-healing, and the fault-tolerant ability of the system is enhanced.

Description

technical field [0001] The invention belongs to the technical field of FPGA reliability application, and more specifically relates to an FPGA dynamic reconfiguration controller capable of resisting single event effects. Background technique [0002] SRAM-type FPGA devices are increasingly widely used in the electronic module design of aerospace systems. On the one hand, because SRAM-type FPGAs have high-performance processing capabilities, their abundant resources meet the needs of spacecraft systems with increasingly complex functions. On the other hand, because Its high flexibility and reprogrammable characteristics make it have significant advantages compared with other devices in terms of development cycle and cost. [0003] Since the space environment is full of various high-energy particles, the impact of high-energy particles on electronic equipment in use can induce radiation effects on electronic devices, thereby affecting the normal operation of electronic equipmen...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F15/78
CPCG06F15/7871
Inventor 毕东杰彭礼彪高乐谢永乐李西峰
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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