Polish stop layer for processing semiconductor element arrays
A semiconductor, polishing machine technology, applied in the direction of semiconductor devices, semiconductor/solid state device manufacturing, electrical components, etc., can solve poor property control and shunting, does not provide better control or uniformity of the entire wafer, hinders stubs, etc. question
Active Publication Date: 2021-10-29
INTEGRATED SILICON SOLUTION CAYMAN INC
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Problems solved by technology
[0008] These disadvantages cause widespread problems for the incorporation of MRAM into MTJ columns
Damage and non-uniformity lead to problematic tunneling magnetoresistance (“TMR”) values, poor property control and shunting
The inability to terminate the CMP process precisely at the right time prevents stubs needed for higher density arrays using MRAM
Alternative etch processes do not provide better control or uniformity across wafers
Method used
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Embodiment Construction
[0048] Methods of fabricating semiconductor devices are disclosed herein that can be used in fabricating MRAM devices using MTJs. Each of the features and teachings disclosed herein can be utilized alone or in combination with other features and teachings. Representative examples utilizing many of the other additional features and teachings, both alone and in combination, are described in further detail with reference to the accompanying drawings. This detailed description is only intended to teach those skilled in the art other details for practicing preferred aspects taught by the present invention and is not intended to limit the scope of the claims. Thus, combinations of features disclosed in the following Detailed Description may not be necessary to practice the teachings in the broadest sense, but are taught only to particularly describe representative examples of the teachings of the present invention.
[0049] In the following description, for purposes of explanation ...
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Abstract
The described embodiments can be used in semiconductor manufacturing and employ materials with high and low polishing rates to help determine a precise polishing endpoint that is consistent across the wafer and can stop polishing before damaging the semiconductor elements. The height of the low polishing rate material between the semiconductor elements is used as the polishing end point. Since the low polishing rate material slows down the polishing process, it is easy to determine the endpoint and avoid damage to the semiconductor element. Another or alternative etch endpoint may be a thin layer of material that, when exposed, provides a very sharp spectral signal, allowing the etch process to stop.
Description
technical field [0001] The present invention relates generally to the field of semiconductor fabrication, and more particularly to forming and / or exposing semiconductor elements on wafers using chemical mechanical polishing. Background technique [0002] The methods described in the examples can be used to form, separate and expose the semiconductor elements on the microchip wafer. In particular, the method can be used to separate and expose arrays of magnetic tunnel junction (MTJ) pillars. [0003] MTJs are semiconductor devices that may contain two ferromagnetic bodies separated by an insulator. In the case of a magnetoresistive random access memory (MRAM) device, an MTJ may include a free magnetic layer and a reference magnetic layer, each separated by an insulator. Other layers are used to create memory cells, such as MRAM devices. The MTJ of an MRAM device may also include a hard mask over the magnetic layer. [0004] MRAM is able to store information because the re...
Claims
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IPC IPC(8): H01L43/12H01L43/02H01L43/10B24B37/22B24B37/24H10N50/01H10N50/10H10N50/80
CPCH10B61/00H10N50/10H10N50/01H01L21/304H10N50/80
Inventor M·M·皮纳尔巴锡J·A·埃尔南德斯A·达塔M·J·加耶克P·B·赞泰伊
Owner INTEGRATED SILICON SOLUTION CAYMAN INC