Silicon-based fan-out package of integrated heat-dissipation structure and wafer-level packaging method

Abstract

The invention discloses a silicon-based fan-out package of an integrated heat-dissipation structure and a wafer-level packaging method. Based on a silicon-based fan-out package technology, a heat-dissipation structure is directly formed on a second surface of a silicon substrate after a chip is embedded. A wafer-level process is used for manufacturing, the machining is high-precision, the processis simple, and the price is low. Compared with conventional mechanically processed heat sinks, the silicon-based fan-out package can use a silicon micromachining process directly on a silicon substrate to produce a finer heat dissipation structure, create a larger heat dissipation area within the same unit volume, and achieve better heat radiation. This heat dissipation structure is directly integrated on the backside of a chip embedded in a silicon substrate, and has a high integration density, a small size, and a light weight. In addition, the interface between the external environment and the chip is reduced, and the heat dissipation effect is further improved. Preferably, a heat-dissipating cover plate with forced water cooling can be integrated on the heat dissipation structure of thesecond surface of the silicon substrate to obtain better heat dissipation efficiency.

Description

technical field [0001] The invention relates to the technical field of semiconductor packaging, in particular to a silicon-based fan-out packaging with an integrated heat dissipation structure and a wafer-level packaging method. Background technique [0002] Wafer-level fan-out packaging refers to reconfiguring the wafer and wafer-level rewiring method, and the I / O is covered with the rewiring surface array to cover the packaging surface, so as to expand the I / O pitch and meet the requirements of the next level of interconnection. pitch requirements. [0003] At present, in the traditional fan-out packaging technology typically represented by eWLB, the five sides of the chip are wrapped with an epoxy molding compound. However, plastic encapsulation materials generally have poor thermal conductivity, so that the heat dissipation efficiency of the chip is low, and an additional integrated heat dissipation structure is required, but the integration of the additional heat dissi...

AI Technical Summary

Problems solved by technology

However, plastic encapsulation materials generally have poor thermal conductivity, which makes the heat dissipation efficiency of the chip lower, requiring an additional integrated heat dissipation structure, but the integration of the additional heat dissipation structure is more complicated and the production cost is high

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