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Chip packaging structure and method of integrated passive element

A chip packaging structure and passive component technology, applied in electrical components, electrical solid devices, semiconductor devices, etc., can solve the problems of low integration and large thickness of semiconductor packaging components, and achieve improved heat dissipation performance, high stability, and reliable coupling. high sex effect

Inactive Publication Date: 2018-05-01
NAT CENT FOR ADVANCED PACKAGING
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] Therefore, the technical problem to be solved by the present invention is to solve the problem that the integration degree of the passive elements in the semiconductor package assembly is low, and the thickness of the semiconductor package assembly with multiple passive elements is relatively large.

Method used

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  • Chip packaging structure and method of integrated passive element
  • Chip packaging structure and method of integrated passive element
  • Chip packaging structure and method of integrated passive element

Examples

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Embodiment 1

[0036] The embodiment of the present invention improves a chip package structure integrating passive components, such as figure 1 As shown, it includes: a package body 1 with a chip 2 packaged inside; the device surface of the chip 2 is located on the same plane as the first surface of the package body 1; the passive element layer 3 is arranged on the second surface of the package body 1; the first insulating Layer 4 is arranged on the passive element layer 3; the conductive column 5 is arranged in the package body 1, one end of the conductive column 5 is coupled with the passive element layer 3, and the other end is located on the same plane as the first surface of the package body 1; The wiring layer 6 is disposed on the first surface of the package body 1 and coupled with the chip 2 and the conductive pillar 5 . In this embodiment, the device surface of the chip 2 refers to the plane where the pads of the chip 2 are located, and the device surface of the chip 2 is located o...

Embodiment 2

[0051] This embodiment provides a chip packaging method for integrating passive components, such as Figure 5 shown, including the following steps:

[0052] Step S1: providing a substrate, and forming an adhesive layer on the substrate. like Figure 6 As shown, in a specific embodiment, the material of the substrate 7 can be glass or ceramics, etc., and the material of the adhesive layer 8 can be thermal peeling adhesive or UV adhesive film, etc. In a specific embodiment, spray coating, spin coating or film sticking can be used and so on to form the adhesive layer 8 on the substrate 7 .

[0053] Step S2: Paste the device surface of the chip on the pasting layer. like Figure 7 As shown, in this embodiment, the device surface of the chip 2 refers to the plane where the pads of the chip 2 are located. In a specific embodiment, there may be one or more chips 2, and the number of chips 2 is determined according to the needs of actual application scenarios.

[0054] Step S3: ...

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Abstract

The invention discloses a chip packaging structure and method of an integrated passive element. The chip packaging structure of the integrated passive element comprises a packaging body, a passive element layer, a first insulating layer, a conductive column, a rewiring layer, wherein a chip is packaged in the packaging body; a device surface of the chip and a first surface of the packaging body are located at the same plane; the passive element layer is arranged at a second surface of the packaging body; the first insulating layer is arranged on the passive element layer; the conductive columnis arranged in the packaging body, one end of the conductive column is coupled to the passive element layer, and the other end of the conductive column is located at the same plane with the first surface of the packaging body; and the rewiring layer is arranged at the first surface of the packaging body and is coupled to the chip and the conductive column. The chip packaging structure is providedwith the passive element layer at the second surface of the packaging body, thereby solving a problem of great thickness of the chip packaging structure integrated with a plurality of passive elements due to embedment of the passive elements in the rewiring layer in the prior art, and reducing the thickness of the packaging structure of the plurality of passive elements.

Description

technical field [0001] The invention relates to the technical field of semiconductor packaging, in particular to a chip packaging structure and packaging method for integrating passive components. Background technique [0002] With the increasing integration of electronic devices, a system-in-package (SIP) has been proposed in the field of semiconductor packaging, which integrates multiple active electronic components with different functions and optional passive devices, and Other devices such as micro-electro-mechanical systems (Micro-Electro-Mechanical System, MEMS) or optical devices are first assembled together to achieve a single standard package with certain functions, thus forming a system or subsystem. [0003] The method widely used at present is to integrate packaged passive devices and other types of bare chips or packaged chips into one package through secondary packaging to achieve the effect of increasing the integration level. However, this method requires a...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L25/16H01L23/48H01L23/367H01L23/522H01L23/528H01L21/50
CPCH01L23/528H01L25/16H01L21/50H01L23/367H01L21/56H01L21/76877H01L23/488H01L23/31H01L23/5223H01L23/5227H01L23/5228H01L24/02H01L2221/1068H01L2224/0231H01L2224/0237H01L2224/02379H01L2224/18H01L2224/24137H01L2224/12105
Inventor 姚大平
Owner NAT CENT FOR ADVANCED PACKAGING
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