Process for protecting side wall in high-aspect-ratio channel hole etching
A high-aspect-ratio, channel-based technology, applied to electrical components, electrical solid-state devices, circuits, etc., can solve problems such as performance degradation, electrical performance failure, and damage to the functional film of memory cells, so as to improve yield and electrical performance Effect
Active Publication Date: 2018-05-04
YANGTZE MEMORY TECH CO LTD
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Problems solved by technology
For this reason, the plasma will damage the functional film of the memory cell, such as creating vacancies in the functional film, which deteriorates the performance after wet etching and may cause electrical performance failure
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[0025] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided for more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.
[0026] In the interest of clarity, not all features of an actual implementation are described. In the following description, well-known functions and constructions are not described in detail since they would obscure the invention with unnecessary detail. It should be appreciated that in the development of any actual embodiment, numerous implementation details must be worked out to achieve the developer's specific goals, such as ch...
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The invention provides a process for protecting a side wall in high-aspect-ratio channel hole etching. The process comprises the following steps of providing a substrate stack structure; performing etching on the surface of the substrate stack structure to form channel holes; performing depositing and filling in the channel holes to form a channel hole side wall stack structured functional thin film; and depositing a protection film on the surface of the side wall stack structure, and enabling the thickness, on the top of the channel holes, of the protection film to be higher than the thickness, at the bottom of the channel holes, of the protection film. According to the process, the thickness, on the top of the channel holes, of the protection film is higher than the thickness, at the bottom of the channel holes, of the protection film, so that the protection film on the top, particularly the protection film in the upper part opening of the channel holes, is higher in damage resistance in the subsequent dry etching; and when dry etching is completed, residual protection film is still formed, thereby protecting the channel hole side wall stack structured functional thin film from plasma bombardment damage, improving the yield of the channel hole etching process processing, and improving electrical performance of a device.
Description
technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for improving a channel hole etching process in a 3D NAND flash memory structure. Background technique [0002] With the development of planar flash memory, the production process of semiconductors has made great progress. However, in recent years, the development of planar flash memory has encountered various challenges: physical limits, existing development technology limits, and storage electron density limits. In this context, in order to solve the difficulties encountered in planar flash memory and to seek lower production costs per unit storage unit, various three-dimensional (3D) flash memory structures have emerged, such as 3D NOR (3D or not) flash memory and 3D NAND (3D NAND) flash memory. At present, in the development process of 3D NAND, as the number of stacked layers increases, higher requirements are put forward for the preparation processes suc...
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IPC IPC(8): H01L27/11551H01L27/11578H10B41/20H10B43/20
CPCH10B41/20H10B43/20
Inventor 方振王猛刘隆冬苏恒朱喜峰陈保友戴绍龙
Owner YANGTZE MEMORY TECH CO LTD