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A Process for Protecting Sidewalls in High Aspect Ratio Trench Hole Etching

A high aspect ratio, channel technology, used in semiconductor devices, electrical components, circuits, etc., can solve the problems of electrical performance failure, performance deterioration, damage to the functional film of memory cells, etc., to improve electrical performance and improve yield. Effect

Active Publication Date: 2020-07-10
YANGTZE MEMORY TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

For this reason, the plasma will damage the functional film of the memory cell, such as creating vacancies in the functional film, which deteriorates the performance after wet etching and may cause electrical performance failure

Method used

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  • A Process for Protecting Sidewalls in High Aspect Ratio Trench Hole Etching
  • A Process for Protecting Sidewalls in High Aspect Ratio Trench Hole Etching
  • A Process for Protecting Sidewalls in High Aspect Ratio Trench Hole Etching

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Embodiment Construction

[0025] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided for more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0026] In the interest of clarity, not all features of an actual implementation are described. In the following description, well-known functions and constructions are not described in detail since they would obscure the invention with unnecessary detail. It should be appreciated that in the development of any actual embodiment, numerous implementation details must be worked out to achieve the developer's specific goals, such as ch...

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PUM

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Abstract

The present invention provides a process for protecting sidewalls in high aspect ratio channel hole etching, comprising the following steps: providing a substrate stack structure; etching a channel hole on the substrate stack structure; forming a channel hole in the trench Deposit and fill in the channel hole to form a channel hole sidewall stacked structure functional film; deposit a protective film on the surface of the sidewall stacked structure, and make the thickness of the protective film at the top of the channel hole greater than the thickness at the bottom of the channel hole . In the process of the present invention, the thickness of the protective film at the top of the channel hole is greater than that at the bottom of the channel hole; during subsequent dry etching, the protective film at the top, especially the protective film at the upper opening of the channel hole, is more resistant to damage. At the end of dry etching, there is still a protective film remaining, thereby protecting the stacked functional film on the side wall of the channel hole from being damaged by plasma bombardment, improving the yield rate of the channel hole etching process, and improving the electrical properties of the device. performance.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for improving a channel hole etching process in a 3D NAND flash memory structure. Background technique [0002] With the development of planar flash memory, the production process of semiconductors has made great progress. However, in recent years, the development of planar flash memory has encountered various challenges: physical limits, existing development technology limits, and storage electron density limits. In this context, in order to solve the difficulties encountered in planar flash memory and to seek lower production costs per unit storage unit, various three-dimensional (3D) flash memory structures have emerged, such as 3D NOR (3D or not) flash memory and 3D NAND (3D NAND) flash memory. At present, in the development process of 3D NAND, as the number of stacked layers increases, higher requirements are put forward for the preparation processes suc...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/11551H01L27/11578H10B41/20H10B43/20
CPCH10B41/20H10B43/20
Inventor 方振王猛刘隆冬苏恒朱喜峰陈保友戴绍龙
Owner YANGTZE MEMORY TECH CO LTD