Efficient FFT achieving method in MTD wave filter

Abstract

The invention discloses an efficient FFT achieving method in an MTD wave filter and relates to the field of radar digital signal processing. The method includes the following steps that 1, an FFT arithmetic unit is adopted for conducting FFT operation on received data, and the operated data is output into an on-chip storage management unit; 2, the on-chip storage management unit accesses an address sequence of an off-chip memory according to time hopping of a counter and writes the operated data into the off-chip memory; 3, the on-chip storage manage unit writes readback data according to demands, accesses the address sequence of the off-memory according to time hopping of the counter or accesses an address sequence, which is arrayed in a bit-reversed order, of the off-chip memory according to time hopping of the counter, reads back data from the off-chip memory and sends the data to the FFT arithmetic unit. According to the method, an on-chip SRAM memory with the capacity of 8*2Mb issaved, the design scale and power dissipation of a chip are greatly reduced, and the reliability of the chip is improved.

Description

technical field [0001] The invention relates to the field of radar digital signal processing, in particular to a high-efficiency FFT realization method in an MTD filter. Background technique [0002] FFT transform is a very important processing method in radar digital signal processing. In the clutter suppression technology of moving target detection (MTD), which is widely used at present, FFT is the core calculation unit for quickly and successfully detecting the target. [0003] The working block diagram of FFT processing data in the traditional way, including two parts of FFT IP core and data interface. Among them, the FFT IP core in the traditional way includes two parts, the FFT operation module and the inversion memory. After completing the FFT operation on the input natural (inversion) sequence data, the inversion sequence is performed through the inversion memory. After that, it is output to the off-chip memory through the data interface, and the data interface only...

AI Technical Summary

Problems solved by technology

Although the FFT IP core in the traditional way has high computing efficiency, its disadvantage is that when processing each frame of 32K×64bit radar signal data, in order to realize the function of inversion sequence, a 2Mb inversion must be configured on-chip Sequence memory, when 8 FFTs are used for data processing at the same time, the capacity of the inversion sequence memory will be expanded to 16Mb, which will bring about a sharp increase in chip size and power consumption, and greatly reduce the reliability of the chip

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