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System and method for retaining dram data when reprogramming reconfigurable devices with dram memory controllers incorporating a data maintenance block colocated with a memory module or subsystem

A storage controller and data maintenance technology, applied in the fields of electrical digital data processing, instruments, climate sustainability, etc., can solve the problem of long time consumption, achieve the effect of important data persistence and shorten the overall startup time

Pending Publication Date: 2018-07-17
SRC LABS LLC
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  • Description
  • Claims
  • Application Information

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Problems solved by technology

The reason for this is that it takes too much time to copy the entire contents of the DRAM data and save it in another part of the system, reconfigure the processor, and then finally retrieve the data and restore it to DRAM

Method used

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  • System and method for retaining dram data when reprogramming reconfigurable devices with dram memory controllers incorporating a data maintenance block colocated with a memory module or subsystem
  • System and method for retaining dram data when reprogramming reconfigurable devices with dram memory controllers incorporating a data maintenance block colocated with a memory module or subsystem
  • System and method for retaining dram data when reprogramming reconfigurable devices with dram memory controllers incorporating a data maintenance block colocated with a memory module or subsystem

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Embodiment Construction

[0028] now refer to figure 1 , shows a functional block diagram of a computer subsystem 100 including a DRAM memory 102 and a reconfigurable logic device 104 . In a representative embodiment of the invention, reconfigurable logic device 104 may comprise a Field Programmable Gate Array (FPGA). It should be noted, however, that RLD 104 may comprise any and all forms of RLD, including hybrid devices such as RLDs with partial reconfiguration capability or with configurable Application-specific integrated circuit (ASIC) devices in the reprogramming area.

[0029] Also shown is a data maintenance block 106 for preserving the data of the DRAM memory 102 when the logic device 104 is reconfigured during operation of the computer subsystem 100 in accordance with the present invention. In representative embodiments of the present invention, data maintenance block 106 may conveniently be provided as a Complex Programmable Logic Device (CPLD) or other separate integrated circuit device, ...

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Abstract

A system and method for retaining dynamic random access memory (DRAM) data when reprogramming reconfigurable devices with DRAM memory controllers such field programmable gate arrays (FPGAs). The DRAMmemory controller is utilized in concert with a data maintenance block collocated with the DRAM memory and coupled to an I2C interface of the reconfigurable device, wherein the FPGA drives the majority of the DRAM input / output (I / O) and the data maintenance block drives the self-refresh command inputs. Even though the FPGA reconfigures and the majority of the DRAM inputs are tri-stated, the data maintenance block provides stable input levels on the self-refresh command inputs.

Description

[0001] Cross References to Related Applications [0002] This application claims the invention titled "System and Technology for Preserving DRAM Data When Reprogramming a Reconfigurable Device with a DRAM Memory Controller Containing Data Maintenance Blocks Collocated with Memory Modules or Subsystems," filed August 24, 2015. Method", priority of U.S. Patent Application Serial No. 14 / 834,273, issued October 6, 2015, entitled "Preservation of DRAM Data When Reprogramming a Reconfigurable Device with a DRAM Memory Controller System and Method," a continuation-in-part of U.S. Patent No. 9,153,311, the disclosure of which is incorporated herein by reference in its entirety. Background technique [0003] In general, the present invention relates to the field of reconfigurable computing systems. More specifically, the present invention relates to a system and system for preserving dynamic random access memory (DRAM) data when reprogramming a reconfigurable device with a DRAM memory...

Claims

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Application Information

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IPC IPC(8): G06F13/16
CPCG06F13/1668G06F13/1694Y02D10/00
Inventor T·J·特沃特
Owner SRC LABS LLC
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