High speed ADC interweaved sampling system

Abstract

The invention discloses a high speed ADC interweaved sampling system, comprising a differential circuit and a clock circuit. The differential circuit and the clock circuit are connected with ADCs of Nchannels through differential pair transmission lines. The differential circuit comprises a first transformer and a second transformer which are cascaded in sequence, and a signal output module. An input end of the signal output module is connected with an output end of the second transformer. The clock circuit comprises a post-stage clock module which is used for inputting differential pair clock signals into the ADCs of the N channels, and a first clock chip which is used for inputting the differential pair signals with phase difference into the post-stage clock module. The post-stage clockmodule comprises N / 2 second clock chips differentially matching the ADCs of the N channels. The N / 2 second clock chips are connected with the output ends of the first clock chips. According to the system, the deferential signal imbalance can be suppressed, a signal to noise and distortion ratio and a spurious-free dynamic range of the system are improved, and the integrated performance of the system can be improved.

Description

technical field [0001] The invention relates to the field of high-speed data acquisition, in particular to a high-speed ADC interleaved sampling system. Background technique [0002] In the field of wireless communication transmission and reception, the sampling rate of ADC is required to be higher and higher to make it meet the sampling standard of TIADC system. Therefore, it is necessary to modify the front-end circuit of ADC, mainly the power divider and clock circuit. The current power splitter generally uses a single transformer to convert the input single-ended signal into a differential signal, but due to the existence of its internal distributed capacitance, it will cause the imbalance of the differential signal, resulting in harmonic distortion, amplitude attenuation, and phase of the ADC channel. Imbalance, etc.; at present, the clock circuit in this field generally uses an external level to generate a differential clock signal output to the ADC. The external level...

AI Technical Summary

Problems solved by technology

The current power splitter generally uses a single transformer to convert the input single-ended signal into a differential signal, but due to the existence of its internal distributed capacitance, it will cause the imbalance of the differential signal, resulting in harmonic distortion, amplitude attenuation, and phase of the ADC channel. Imbalance, etc.; at present, the clock circuit in this field generally uses an external level to generate a differential clock signal output to the ADC. The external level is unstable, which makes the phase error larger, and further improves the system signal-to-noise ratio (SINAD) and spurious dynamics. The range (SFDR) is greatly reduced; these issues are not conducive to improving the overall performance of the system

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