44results about How to "Second Harmonic Suppression" patented technology

The invention discloses a method for improving efficiency of a wide-band radio frequency power amplifier, namely adding a harmonic source suppression network in output of the wide-band radio frequency power amplifier for improving efficiency. The invention also discloses a circuit structure for improving the efficiency of the wide-band radio frequency power amplifier. The circuit structure disclosed by the invention comprises a wide-band radio frequency power amplifier stage, a wide-band output matching network and a harmonic suppression network, wherein the wide-band output matching network is used for effectively outputting an output signal; the harmonic suppression network is used for carrying out harmonic suppression on a signal input into the wide-band output matching network, and the harmonic suppression network is formed by at least two second harmonic suppression networks which are connected between output of the wide-band radio frequency power amplifier stage and the ground in parallel. The method and the structure for improving the efficiency of the wide-band radio frequency power amplifier have the advantages that a second harmonic suppression circuit is adopted for being independent from an output matching network, a resonant frequency point can be flexibly controlled, second harmonic is effectively suppressed, efficiency and output capability of the power amplifier are improved, and wide-band matching is formed, so that the radio frequency power amplifier can operate in a wide range, and performances of the radio frequency power amplifier are improved.

The invention discloses a simultaneous frequency-doubled and frequency-quadruplicated loop current suppression method suitable for an MMC (Modular Multi-level Converter). The method comprises the steps of extracting current values of upper and lower bridge arms of each phase of the MMC, and calculating a loop current value according to the acquired current values; performing frequency-doubled negative sequence and frequency-quadruplicated positive sequence rotating coordinate transformation on the calculated loop current value to transform frequency-doubled and frequency-quadruplicated components into direct-current components respectively; comparing dq axis components of the transformed frequency-doubled and frequency-quadruplicated components of the loop current with a corresponding loop current dq axis component reference value respectively, and then performing linear adjustment control; introducing voltage feed-forward quantities corresponding to the frequency-doubled and frequency-quadruplicated components to eliminate a dq axis coupling part, then obtaining a dq axis reference value for loop current suppression, performing frequency-doubled negative sequence and frequency-quadruplicated positive sequence inverse transformation on the obtained dq axis reference value respectively, adding the obtained corresponding loop current suppression reference values, and adding the sum to a modulated wave signal. The reference value obtained by frequency-doubled negative sequence rotating coordinate transformation on loop current can effectively suppress second harmonic in the loop current.

The invention discloses a vehicle-mounted multiplex charging machine. The vehicle-mounted multiplex charging machine comprises a high-voltage battery, three inductors L1, L2 and L3, and three IGBT bridge arms in parallel connection mutually. A positive pole of the high-voltage battery is connected with one ends of the inductors L1, L2 and L3 through relay switches S1, S2 and S3. The other ends ofthe inductors L1, L2 and L3 are connected with middle nodes of the three IGBT bridge arms correspondingly. A negative pole of the high-voltage battery is directly connected with a jointly-connecting end of the three IGBT bridge arms. The connecting ends of the relay switches S1 and S2 and the inductors L1 and L2 are a live line connector and a zero line connector of a power grid correspondingly. The two ends of the three IGBT bridge arms in parallel connection mutually are connected with an inverter-motor system. IGBT devices constituting the three IGBT bridge arms are connected and controlledthrough a controller module. When the vehicle-mounted multiplex charging machine works, a Boost working state, a state of single-phase power grid connection to charge the battery, a single-phase grid-connected inversion state, and a vehicle-vehicle mutually-charging state are included. The vehicle-mounted multiplex charging machine adopts different relay switch combinations, equipment can work indifferent states, and different functions are achieved.

Disclosed is an inhibition method for input second-harmonic current of a two-level single-phase inverter. The method is not only capable of inhibiting significantly the input second-harmonic current, but also capable of reducing dependence on a DC busbar filtering capacitor. The method multiplies output inductive current sampling signals of a preceding-stage DC-DC convertor and modulating signals of a DC-DC convertor through a multiplying unit. Output signals of the multiplying unit pass a band-pass filter, and then together with the inductive current sampling signals which pass a follower, are used as feedback signals of a current regulator. Output signals of a voltage regulator are used as a reference of the current regulator. The current regulator generates modulating signals and sends the modulating signals into a PWM modulator and at last through a driving circuit, driving signals which control main power tubes Q1-Qn of a Buck-class DC-DC convertor to work are obtained. The method has the advantages of being capable of directly inhibiting a second-harmonic component of input current of the two-level single-phase inverter, simple in structure of control circuit and convenient to realize and the like.

The invention discloses a full-difference E-type power amplifier. The amplifier is a circuit composed of a Bipolar device, a CMOS device and a passive device, wherein a difference input pair is the Bipolar device; a cross coupling pair is an NMOS tube; the amplifier adopts a two-stage structure, the first pre-amplifying stage performs a pretreatment for an input constant envelope signal so as to meet the requirement for fast opening and closing of the second power amplifying stage; and the cross coupling pair structure is added into each stage so as to accelerate the on/off speed, satisfy high frequency application and reduce the width length ratio of a main switching pipe. Meanwhile, the difference input also avoids the influence of a second harmonic wave on a substrate, completely filters and removes secondary and high and even order harmonic waves and eliminates the substrate coupling such that the device is not easy to puncture. The invention has the following advantages of high power efficiency, low harmonic distortion, low power voltage, simple structure, fast working speed and low power consumption and the like.

The invention discloses a Cascode power amplifier with improved efficiency and linearity, comprising a Cascode structure, an input matching network and an output matching network, wherein the Cascode structure is composed of a grounded-emitter transistor and a grounded base transistor; the input matching network is connected between the signal input port of the power amplifier and the base electrode of the grounded-emitter transistor; the output matching network is connected between the collector electrode of the grounded base transistor and the signal output port of the power amplifier; a first series-parallel resonant network is connected between the collector electrode of the grounded-emitter transistor and the ground; a second series-parallel resonant network is connected between the base electrode of the grounded base transistor and the ground; a secondary harmonic series resonant network is connected between the collector electrode of the grounded base transistor and the ground; a third harmonic parallel resonant network is connected between the collector electrode of the grounded base transistor and the output port. The invention can effectively inhibit even harmonic in the power amplifier output, improves the linear degree of the power amplifier and improves the output power of the power amplifier and the additional efficiency of the power by high-order odd harmonic.

The invention provides a power amplification device of a nonlinear electromagnetic ultrasound exciting signal and relates to the technical field of nonlinear electromagnetic ultrasound non-destructive detection. The device includes a function generator, a first DC biasing circuit, a second DC biasing circuit, a three-winding input transformer, a first AC/DC superposed circuit, a second AC/DC superposed circuit, a first linear power amplification module circuit, a second linear power amplification module circuit, a third linear power amplification module circuit, a fourth linear power amplification module circuit, a high-voltage DC power supply, a three-winding output transformer and an AC coupling circuit. An output signal from the device not only can drive an electromagnetic ultrasound transducer to generate an ultrasound wave having enough acoustic power at fundamental frequency, but also can inhibit even harmonic waves in the driving signal, thereby reducing influence on a detection result due to non-linearity in the exciting circuit.

The invention provides a harmonic suppression system. The harmonic suppression system comprises an interface connector, a baseband chip, an antenna, an antenna switch, at least two LC (inductance capacitance) trapped wave networks, a first differential SPMT (serial port memory technology) switch and a second differential SPMT switch, wherein the interface connector is connected with a common terminal of the first differential SPMT switch; a control port of the first differential SPMT switch is connected with a control port of the second differential SPMT; gating throwing ends of the first differential SPMT switch are respectively connected with one ends of the LC trapped wave networks correspondingly one by one; the control port of the second differential SPMT switch is connected with the baseband chip; the gating throwing ends of the second differential SPMT switch are respectively connected with the other ends of the LC trapped wave networks correspondingly; a common terminal of the second differential SPMT switch is connected with the baseband chip; the baseband chip is connected with the antenna switch; and the antenna switch is connected with the antenna.

The invention discloses a broadband matching circuit for improving harmonic performance, which is connected between a power amplifier stage and a signal output end of a power amplifier. The broadbandmatching circuit comprises a choking coil, at least two second harmonic suppression networks which are respectively resonant at different frequency points, at least two third harmonic suppression networks which are respectively resonant at different frequency points, and a broadband matching network, wherein the choking coil is connected between the output end of the power amplifier stage and a power supply; the at least two second harmonic suppression networks are respectively connected between the output end of the power amplifier stage and the ground, and the output ends of the at least twosecond harmonic suppression networks are connected to the input end of the broadband matching network; the at least two third harmonic suppression networks are respectively connected between the output end of the broadband matching network and the ground, and the output ends of the at least two third harmonic suppression networks are connected to the signal output end of the power amplifier. According to the broadband matching circuit, the resonant frequency points of the second harmonic suppression networks and the third harmonic suppression networks can be flexibly controlled, and the efficiency of the power amplifier is improved.

The invention relates to a microwave integrated circuit chipset technology based on metal carrier plate integration; wherein a plurality of chips, a matching circuit and a biasing circuit are integrated on a metal carrier plate in a high-density manner, and the components are interconnected through gold wires, so that a chipset product with independent functions is realized. According to the invention, the packaging material and the packaging process of the integrated circuit are saved, the raw material is reduced, the size and the weight are greatly reduced, and the cost is reduced. In addition, the carrier plate is welded on the component substrate through the welding flux, so that the problem of temperature rise of the device caused by the increase of the power density of the power amplifier along with the development of the technology is greatly relieved.

The invention belongs to the technical field of integrated circuit design, and particularly relates to an eight-path power synthesis harmonic control circuit suitable for a radio frequency power amplifier. The radio frequency power amplifier is composed of a first-stage power pre-amplification circuit, a second-stage power pre-amplification circuit and an output-stage main power amplification circuit. The main power amplification circuit is composed of a power amplification circuit, an eight-path current-voltage mode power synthesis 1: 2 on-chip transformer and a harmonic control circuit. Thepower amplification circuit is composed of a blocking capacitor, a bias resistor and an NMOS power tube. According to the transformer, under the condition that the optimal load impedance is not changed, a plurality of high-output-power amplifying circuits are additionally arranged, the influence caused by parasitic capacitance is relieved, the output power is remarkably improved, and the high output power which is very difficult to achieve through the CMOS technology is achieved. According to the scheme, the multiple power amplification stages are connected, the output power can be remarkablyimproved, and the power amplifier can be used as a radio frequency power amplifier and can also be applied to multiple devices with the power amplification function.

The invention provides a semiconductor device. In a related-art semiconductor device, there is a problem that a second-order harmonic distortion originating in a power amplifier driven by a rectangular-wave signal cannot be effectively suppressed. According to an embodiment, a semiconductor device generates a transmission signal (RF_OUT) for driving an antenna by receiving first transmission pulses (INd_P) and second transmission pulses (INd_N) having a duty ratio lower than 50%, adjusting a phase difference between the first transmission pulses (INd_P) and the second transmission pulses (INd_N) to a predefined phase difference, and supplying the first transmission pulses (INd_P) and the second transmission pulses (INd_N) after phase difference-adjustment to a power amplifier (54).

The invention discloses a microstrip antenna with a harmonic suppression function, which comprises a dielectric substrate and an antenna unit, and the antenna unit comprises an antenna patch and a microstrip feeder line, and the antenna patch is pasted and fixed on the dielectric substrate; the microstrip feeder line is connected with the middle part of one side of the antenna patch, two U-shapedholes, namely a first U-shaped hole and a second U-shaped hole, are distributed in the microstrip feeder line along the length direction of the microstrip feeder line, the length of the first U-shapedhole is smaller than that of the second U-shaped hole, and the opening directions of the two U-shaped holes both face the direction of the antenna patch. According to the invention, second harmonicsand third harmonics can be effectively suppressed, so that the radiation efficiency of the microstrip antenna is greatly improved.

The invention relates to a control signal generation method of a power factor correction circuit, a control device and a power supply. The control signal generation method comprises the steps of: carrying out zero-crossing detection on an AC voltage of an input AC, and detecting an output voltage of the power factor correction circuit when the AC voltage is detected to be zero-crossing, so as to obtain a detection voltage; and when the detection voltage is between a first preset voltage and a second preset voltage, in a time period between the Kth zero crossing and the (K+1) th zero crossing of the AC voltage, utilizing the control device to adjust a duty ratio and output a control signal based on the detection voltage obtained by the Kth zero crossing, so as to control the power factor correction circuit to carry out power factor correction. According to the control signal generation method, the second harmonic can be suppressed, so that the total harmonic distortion is improved, the dynamic response is improved, the PFC output fluctuation is reduced, the PFC works stably, and stable and accurate output voltage is output.