Manufacturing method of back of RC-IGBT device

Abstract

The invention belongs to the technical field of manufacturing of a semi-conductor device, and relates to a manufacturing method of the back of an RC-IGBT device. A back technology is completed throughinjecting and high temperature annealing on the front of the RC-IGBT device. By means of the manufacturing method, the technology machining difficulty of the device can be effectively lowered, the fragment rate is lowered, and device parameters Vce are also increased; meanwhile, the manufacturing technology is compatible with the front of an existing IGBT, and the product technology cost is not increased.

Description

technical field [0001] The invention relates to a method for fabricating the back surface of an RC-IGBT (Reverse Conducting-IGBT, ie reverse conducting IGBT) device, belonging to the technical field of semiconductor device manufacturing. Background technique [0002] At present, there are two main ways to process the back of RC-IGBT. One is to use Taico technology to prepare ultra-thin sheets, and then do back injection to form N+buffer layer, N+ embedded layer and P+ hole injection layer (P+ layer layer). The liner process is used to bond the processed liner to the silicon substrate on the front side of the device, and then the positive film is thinned and implanted on the back to form an N+buffer layer, an N+ embedded layer and a P+ hole injection layer (P+ layer layer), and finally thermally peel off the positive film and the liner. The first method requires the use of Taico equipment, which is expensive and many foundries do not have this condition at present. Fragmenta...

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Problems solved by technology

[0002] At present, there are two main ways to process the back of RC-IGBT. One is to use Taico technology to prepare ultra-thin sheets, and then do back injection to form N+buffer layer, N+ embedded layer and P+ hole injection layer (P+ layer layer). The liner process is used to bond the processed liner to the silicon substrate on the front side of the device, and then the positive film is thinned and implanted on the back to form an N+buffer layer, an N+ embedded layer and a P+ hole injection layer (P+ layer layer), and finally thermally peel off the positive film and the liner. The first method requires the use of Taico equipment, which is expensive and many foundries do not have this condition at present. Fragmentation risk. In addition, at this time, the front process has been completed, so high-temperature annealing cannot be performed to activate the implanted impurities on the back, resulting in low activation efficiency and high Vce

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