Vertical nanowire transistor and its fabrication method

Abstract

The application provides a vertical nano wire transistor and a manufacturing method thereof; the method comprises the following steps: S1, providing a base including a substrate and a plurality of nano wires arranged on the substrate at intervals, wherein each nano wire comprises sub-nano wires, and each sub-nano wire comprises a first end, a middle portion and a second end; S2, forming a gate medium layer and a grid electrode; S3, forming an interlayer medium layer on the surface of the substrate; S4, forming mutually separated a first contact hole and a second contact hole in the interlayermedium layer, wherein the first contact hole is connected with the side face of the first end, and the second contact hole is connected with the side face of the second end; S5, filling the first contact hole and / or second contact hole with a heavily doped material, carrying out high temperature annealing diffusion and transverse doping, and forming a drain region and / or a source zone. The manufacturing method uses the transverse diffusion method to form evenly doped source region and / or drain region, thus providing a simple and easily controlled vertical nano wire transistor source / drain region doping process.

Description

technical field [0001] The present application relates to the field of semiconductors, in particular, to a vertical nanowire transistor and a manufacturing method thereof. Background technique [0002] The miniaturization of CMOS integrated circuits continues to develop, and the device structure has changed from a two-dimensional planar structure (2D planar) to a three-dimensional Fin Field Effect Transistor (3D Fin Field Effect Transisitor, referred to as 3D Fin FET), and then to a three-dimensional horizontal structure of a ring-gate nanowire field. Effect Transistor (3D Lateral Gate-All-Around Nanowire Field Effect Transisitor referred to as 3D Lateral NW FET), in the future, for higher integration, it will develop into a three-dimensional vertical structure ring gate nanowire field effect transistor (3D Vertical Gate-All-Around Nanowire Field Effect Transisitor, referred to as 3D Vertical NW FET or vertical nanowire transistor). The vertical nanowire transistor can bett...

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Problems solved by technology

[0006] The main purpose of this application is to provide a vertical nanowire transistor and its fabrication method to solve the problem of complicated doping process of source and drain regions in the prior art

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