A test structure and method for extracting finfet parasitic resistance model

Abstract

The invention discloses a test structure and method for extracting a FinFET parasitic resistance model. The test structure includes a FinFET device and a first lead-out electrode V1 located in the source-drain region between two outermost adjacent gates at both ends of the FinFET device. , the second lead-out electrode V2, the third lead-out electrode I and the fourth electrode GND in the source and drain regions outside the outermost gate of the FinFET device, the first lead-out electrode V1, the second lead-out electrode V2, the third lead-out electrode The lead-out electrode I and the fourth electrode GND constitute the four terminals of the Kelvin test. The invention takes the BSIMCMG intensive model as the core, and realizes the extraction of the FinFET parasitic resistance model through the sub-circuit structure. The model structure is simple, and the model parameter extraction and fitting methods are also very convenient. The library files are very close to facilitate subsequent design calls and have very important application prospects.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a test structure and method for extracting a FinFET parasitic resistance model. Background technique [0002] With the continuous shrinking of semiconductor process technology nodes, traditional planar MOSFETs have encountered more and more technical challenges. As a new type of three-dimensional device structure, FinFETs can greatly improve the device characteristics of MOSFETs, including the suppression of short channel effects (SCE ), reduce device leakage, increase drive current, and improve subthreshold characteristics, etc. At present, the world's leading semiconductor foundries have taken the lead in mass-producing FinFET technology in their 16 / 14nm and below process nodes. But despite this, research on FinFET-related processes, devices, and models is still in-depth, and it is expected to further enhance the application value of FinFET technology through continuous ...

AI Technical Summary

Problems solved by technology

[0004] For the model development of FinFET devices, the current mainstream technology in the industry is based on the BSIMCMG model developed by the University of California, Berkeley. However, the BSIMCMG model itself is too simplified for the modeling of parasitic resistance / capacitance, and it is difficult to meet the actual FinFET device model. Therefore, in the model technology research of FinFET devices, the research on the model method of parasitic resistance / capacitance has always been a hot spot of attention, and it is also one of the difficulties in the development of FinFET device models.

At present, there is still no ideal solution for the parasitic resistance model of FinFET devices in the world. Many research results are to divide the parasitic resistance and perform numerical calculation or simulation separately. The main defect is that it is difficult to cross-validate with the measured data. And it is difficult to transplant to the model library file based on BSIMCMG, so it is difficult to apply to the actual circuit simulation

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