A cmp simulation method and simulation system for multilayer interconnect structure

Abstract

The present invention provides a CMP simulation method and simulation system for a multi-layer interconnect structure, comprising: acquiring layout data of a chip, the layout data including interconnect lines from the first layer to the nth layer arranged in sequence from bottom to top The surface topography data of the layer interconnect line, n is an integer greater than or equal to 2; CMP simulation is performed on the first layer interconnect line to obtain the CMP simulation result of the first layer interconnect line; The interconnection wire carries out CMP simulation, obtains the CMP simulation result of described i-th layer interconnection wire, and according to the overlapping type of described i-th layer interconnection wire and the i-1th layer interconnection wire, described i-th layer interconnection wire. The CMP simulation result of the connection is corrected, where i is an integer, and i takes values ​​between 2 and n in sequence, which can not only eliminate the influence of the stacking effect through the correction, make the simulation results accurate and credible, but also make the simulation process more accurate. Simple and fast.

Description

technical field [0001] The invention relates to the technical field of chemical mechanical polishing, in particular to a CMP simulation method and simulation system of a multilayer interconnection structure. Background technique [0002] Chemical Mechanical polishing (CMP), as a key technology to achieve global planarization of the chip surface and a core technology to support manufacturability design process optimization, plays an important role in the design and manufacture of integrated circuits. Because the factors affecting the CMP process are very complex, it is necessary to simulate the CMP process of the metal interconnection in the chip design layout to obtain the thickness distribution of different regions to guide the subsequent redundant metal filling and optimize the CMP process. flatness. More importantly, it can also be used for subsequent manufacturability design analysis, full-chip parasitic parameter extraction and timing analysis, etc., and then can judge...

AI Technical Summary

Problems solved by technology

[0003] At present, the metal interconnection lines in the chip are mostly multi-layer structures, but the existing CMP simulation methods are all algorithms for the single-layer interconnection structure, and there is no public simulation method for the multi-layer interconnection structure.

If the simulation method of the single-layer interconnection structure is directly applied to the multi-layer interconnection structure, the calculation results cannot reflect the mutual influence between layers in the multi-layer interconnection structure, that is, the stacking effect cannot be reflected. influences

Moreover, for a multilayer interconnection structure with a more complex process, the process difference of a single layer is enlarged by the accumulation of multiple layers, which makes the surface morphology of the multilayer interconnection structure more influential factors and process control becomes more difficult. , therefore, there is an urgent need for a CMP simulation method for multi-layer metal interconnection structure to predict the manufacturability design

Images