Memory element and manufacturing method thereof
A technology for memory components and manufacturing methods, applied in read-only memory, static memory, semiconductor/solid-state device manufacturing, etc., capable of solving problems affecting the operation of memory components, gate resistance differences, etc.
Active Publication Date: 2020-06-16
MACRONIX INT CO LTD
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[0004] However, in view of the characteristics of the etching process, the grooves used to define the ridge-shaped multilayer stack usually have a profile that is wide at the top and narrow at the bottom, which makes the conduction of the gate electrode of the memory cell in the ridge-shaped multilayer stack Stripes, showing the phenomenon that the width dimension of the lower layer is smaller than the width dimension of the upper layer, resulting in a difference in the gate resistance of memory cells located at different levels in the same memory cell string, which in turn affects the operation of the memory element
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[0029] This specification provides a method for defining critical dimensions of memory elements, which can improve the reliability and operational performance of existing memory elements. In order to make the above-mentioned embodiment and other objectives, features and advantages of this specification more comprehensible, a memory device and its manufacturing method are listed as a preferred embodiment below, and are described in detail with the accompanying drawings.
[0030] However, it must be noted that these specific implementation cases and methods are not intended to limit the present invention. The invention can still be implemented with other features, elements, methods and parameters. The proposal of the preferred embodiment is only used to illustrate the technical characteristics of the present invention, and is not intended to limit the scope of the patent application of the present invention. Those skilled in the art will be able to make equivalent modifications...
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A memory element, including semiconductor substrates, multi -layer stack structures, multiple storage units, contact plugs, and dielectric layers.The multi -layer stack structure includes multiple conductive layers and multiple insulation layers stacked stacked on the semiconductor substrate.The storage unit is formed on these conductors.Contact plugs through these conductor layers and insulation layers.The dielectric layer is located in a multi -layer stack structure, and includes multiple extension parts, which are extended between the adjacent two of these insulating layers to isolate and contact these conductive layers.The size of one of the materials is less than the size near the semiconductor substrate.
Description
technical field [0001] The invention relates to a memory element and a manufacturing method thereof. In particular, it relates to a non-volatile memory (Non-Volatile Memory, NVM) and a manufacturing method thereof. Background technique [0002] Non-volatile memory devices, such as flash memory, have the property of not losing information stored in memory cells when power is removed. It has been widely used in solid-state mass storage applications for portable music players, mobile phones, digital cameras, etc. Three-dimensional non-volatile memory elements, such as vertical-channel (Vertical-Channel, VC) three-dimensional flash memory elements, have a stacked structure of many layers, which can achieve higher storage capacity, and also have excellent electronic characteristics, such as good data retention reliability and speed of operation. [0003] A method for forming a typical three-dimensional nonvolatile memory device includes the following steps: firstly, a multi-la...
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IPC IPC(8): H01L27/11578H01L27/11551H01L21/768G11C16/02H10B43/20H10B41/20
CPCG11C16/02H01L21/768H10B41/20H10B69/00
Inventor 廖廷丰林怡婷
Owner MACRONIX INT CO LTD