Application verification system and verification method of massive information processor

Abstract

An application verification system and a verification method for a massive information processor, the verification system includes an FPGA interconnected with 1601P, and the 1601P is interconnected with the FPGA, and part of the RapidIO channels of the two devices are drawn out through high-speed connectors to realize 4-way Application and verification of different working modes of 4X RapidIO. DDR2+SDRAM and DDR3+SDRAM are used in 1601P application verification to complete the application verification that the interface is compatible with DDR2 / DDR3. The PIU and EMIF function pins are integrated on the 1601P. The PIU and EMIF function pins are connected to FPGA and PROM respectively, and the main control processor is designed in FPGA to realize the verification of PIU function; the EMIF interface is connected to FLASH to perform FLASH and EDAC function verification. The function of the application verification system is maximized.

Description

technical field [0001] The invention belongs to the field of integrated circuit development, and relates to an application verification system and a verification method of a massive information processor. Background technique [0002] 1601P is a normal 17-core processor, integrating PPC core and 16 DSP cores with independent instruction sets, interconnected through the network on chip, and integrating multiple functional modules such as QDR, DDR, PIU / EMIF and RapidIO on the network on chip or high-speed communication interface. However, the existing application verification board for the initial sample verification chip 1601C cannot carry out application verification for 1601P due to its limited design functions. The functional block diagram of the 1601C application verification board is as follows figure 1 shown. [0003] The previous design structure mainly has the following problems: First, the 1601C application verification board realizes the interconnection test betwe...

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Problems solved by technology

However, the existing application verification board for the initial sample verification chip 1601C cannot carry out application verification for 1601P due to its limited design functions. The functional block diagram of the 1601C application verification board is as follows figure 1 shown

[0003] The previous design structure mainly has the following problems: First, the 1601C application verification board realizes the interconnection test between 1601C and 4-way 1X RapidIO of TMS320C6678 through the VPX connector. Meet the application verification of 1601P's 4-way 4X RapidIO; secondly, 1601P integrates the PPC processor core on the basis of 1601C, and designs a memory controller interface compatible with DDR2 / DDR3. The application verification board of 1601C is only designed for DDR3 The verification of the memory controller interface cannot cover the application verification of DDR2 / DDR3 compatibility; finally, the 1601C application verification board is connected to the PROM at the EMIF interface for the application verification of the low-speed memory interface, which cannot satisfy the PIU / EMIF pin multiplexing of 1601P Case

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